[U-Boot] [PATCH v2 21/28] exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices

[Christophe Ricard]

Hi Simon,

This one looks good to me.

Acked-by: Christophe Ricard<christophe-h.ricard at st.com>

Best Regards
Christophe

On 23/08/2015 02:31, Simon Glass wrote:
> Add a TPM node to the various Chromebooks so that driver can be converted to
> driver model.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v2:
> - Add tpm device tree node for panther also
>
>   arch/arm/dts/exynos5250-snow.dts      | 9 +++++++++
>   arch/arm/dts/exynos5250-spring.dts    | 8 ++++++++
>   arch/arm/dts/exynos5420-peach-pit.dts | 6 +++---
>   arch/arm/dts/exynos5800-peach-pi.dts  | 6 +++---
>   arch/x86/dts/chromebook_link.dts      | 5 +++++
>   arch/x86/dts/chromebox_panther.dts    | 5 +++++
>   6 files changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
> index 32c0098..bda5499 100644
> --- a/arch/arm/dts/exynos5250-snow.dts
> +++ b/arch/arm/dts/exynos5250-snow.dts
> @@ -206,6 +206,15 @@
>   		};
>   	};
>   
> +	i2c at 12C90000 {
> +		clock-frequency = <100000>;
> +		tpm at 20 {
> +			reg = <0x20>;
> +			u-boot,i2c-offset-len = <0>;
> +			compatible = "infineon,slb9635tt";
> +		};
> +	};
> +
>   	spi at 12d30000 {
>   		spi-max-frequency = <50000000>;
>   		firmware_storage_spi: flash at 0 {
> diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
> index 76d5323..81b3d29 100644
> --- a/arch/arm/dts/exynos5250-spring.dts
> +++ b/arch/arm/dts/exynos5250-spring.dts
> @@ -59,6 +59,14 @@
>   					 <&gpy4 2 0>;
>   	};
>   
> +	i2c at 12C90000 {
> +		clock-frequency = <100000>;
> +		tpm at 20 {
> +			reg = <0x20>;
> +			compatible = "infineon,slb9645tt";
> +		};
> +	};
> +
>   	mmc at 12200000 {
>   		samsung,bus-width = <8>;
>   		samsung,timing = <1 3 3>;
> diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
> index 2d2b7c9..16d52f4 100644
> --- a/arch/arm/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/dts/exynos5420-peach-pit.dts
> @@ -197,9 +197,9 @@
>   
>   	i2c at 12E10000 { /* i2c9 */
>   		clock-frequency = <400000>;
> -                tpm at 20 {
> -                        compatible = "infineon,slb9645tt";
> -                        reg = <0x20>;
> +		tpm at 20 {
> +			compatible = "infineon,slb9645tt";
> +			reg = <0x20>;
>   		};
>   	};
>   
> diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
> index 600c294..1d7ff23 100644
> --- a/arch/arm/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/dts/exynos5800-peach-pi.dts
> @@ -72,9 +72,9 @@
>   
>   	i2c at 12E10000 { /* i2c9 */
>   		clock-frequency = <400000>;
> -                tpm at 20 {
> -                        compatible = "infineon,slb9645tt";
> -                        reg = <0x20>;
> +		tpm at 20 {
> +			compatible = "infineon,slb9645tt";
> +			reg = <0x20>;
>   		};
>   	};
>   
> diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
> index ad390bf..4291141 100644
> --- a/arch/x86/dts/chromebook_link.dts
> +++ b/arch/x86/dts/chromebook_link.dts
> @@ -237,6 +237,11 @@
>   		};
>   	};
>   
> +	tpm {
> +		reg = <0xfed40000 0x5000>;
> +		compatible = "infineon,slb9635lpc";
> +	};
> +
>   	microcode {
>   		update at 0 {
>   #include "microcode/m12306a9_0000001b.dtsi"
> diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
> index 84eae3a..36feb96 100644
> --- a/arch/x86/dts/chromebox_panther.dts
> +++ b/arch/x86/dts/chromebox_panther.dts
> @@ -62,4 +62,9 @@
>   		};
>   	};
>   
> +	tpm {
> +		reg = <0xfed40000 0x5000>;
> +		compatible = "infineon,slb9635lpc";
> +	};
> +
>   };