[U-Boot] [PATCH v3 4/4] x86: minnowmax: initialize the pin-muxing from device tree

Simon Glass sjg at chromium.org
Thu Jun 4 11:28:46 CEST 2015


Hi Gabriel,

On 26 May 2015 at 08:41, Gabriel Huau <contact at huau-gabriel.fr> wrote:
> Hi Andy,
>
> On 05/26/2015 01:01 AM, Andy Pont wrote:
>>
>> Hi Gabriel,
>>
>>
>>>           soc_gpio_s5_0 at 0 {
>>>               gpio-offset = <0x80 0>;
>>>               pad-offset = <0x1d0>;
>>>               mode-gpio;
>>>               output-value = <0>;
>>>               direction = <PIN_OUTPUT>;
>>>           };
>>>
>>>           soc_gpio_s5_1 at 0 {
>>>               gpio-offset = <0x80 1>;
>>>               pad-offset = <0x210>;
>>>               mode-gpio;
>>>               output-value = <0>;
>>>               direction = <PIN_OUTPUT>;
>>>           };
>>>
>>>           soc_gpio_s5_2 at 0 {
>>>               gpio-offset = <0x80 2>;
>>>               pad-offset = <0x1e0>;
>>>               mode-gpio;
>>>               output-value = <0>;
>>>               direction = <PIN_OUTPUT>;
>>>           };
>>>
>>> And after, you can use the GPIO commands:
>>>
>>> => gpio set E0
>>> gpio: pin E0 (gpio 128) value is 1
>>> => gpio clear E0
>>> gpio: pin E0 (gpio 128) value is 0
>>> => gpio set E2
>>> gpio: pin E2 (gpio 130) value is 1
>>> => gpio clear E2
>>> gpio: pin E2 (gpio 130) value is 0
>>>
>>> E0 E1 and E2 correspond to the GPIO0 1 and 2.
>>
>> Is there, or can someone add, some documentation somewhere as to how to
>> convert between the device tree definition and the value used for "pin" in
>> the gpio commands as it doesn't seem intuitive or obvious to me that what
>> you have defined translates to E0, E1 and E2.
>
> I agree, but I think the documentation should be part of another patch,
> especially as this is the case for all the x86 platform.
> The naming is not specific to the minnowboard max (baytrail).

Sounds good, please go ahead.

Regards,
Simon


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