[U-Boot] [Patch V4 1/7] pci/layerscape: add support for LS1043A PCIe LUT register access

[York Sun]

On 11/11/2015 01:58 AM, Gong Qianyu wrote:
> From: Mingkai Hu <Mingkai.Hu at freescale.com>
> 
> The endian and base address of PEX LUT register region is different
> between Chassis 2 and Chassis 3, so move the base address definition
> to chassis specific header file and add pex_lut_* functions to access
> LUT register.
> 
> Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at freescale.com>
> ---
> V4:
>  - Use #ifndef CONFIG_LS102XA instead of #ifdef CONFIG_FSL_LAYERSCAPE.
> V3:
>  - No change.
> V2:
>  - Fix compile errors for ls1021a.
> 
>  arch/arm/include/asm/arch-fsl-layerscape/config.h      |  2 ++
>  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  4 ++++
>  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  4 ++++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h         |  8 ++++++++
>  drivers/pci/pcie_layerscape.c                          | 14 +++++++-------
>  5 files changed, 25 insertions(+), 7 deletions(-)

Applied to fsl-qoriq master. Thanks.

York