[U-Boot] [PATCH 7/8] x86: queensbay: Really disable IGD

[Simon Glass]

On 22 October 2015 at 19:39, Bin Meng <bmeng.cn at gmail.com> wrote:
> According to Atom E6xx datasheet, setting VGA Disable (bit17)
> of Graphics Controller register (offset 0x50) prevents IGD
> (D2:F0) from reporting itself as a VGA display controller
> class in the PCI configuration space, and should also prevent
> it from responding to VGA legacy memory range and I/O addresses.
>
> However test result shows that with just VGA Disable bit set and
> a PCIe graphics card connected to one of the PCIe controllers on
> the E6xx, accessing the VGA legacy space still causes system hang.
> After a number of attempts, it turns out besides VGA Disable bit,
> the SDVO (D3:F0) device should be disabled to make it work.
>
> To simplify, use the Function Disable register (offset 0xc4)
> to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
> two devices will be completely disabled (invisible in the PCI
> configuration space) unless a system reset is performed.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
>  arch/x86/cpu/queensbay/tnc.c              | 26 ++++++++++++++++++++------
>  arch/x86/include/asm/arch-queensbay/tnc.h |  7 +++----
>  2 files changed, 23 insertions(+), 10 deletions(-)

Nice debugging!

Acked-by: Simon Glass <sjg at chromium.org>