[U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel

Marek Vasut marex at denx.de
Thu Sep 3 11:37:43 CEST 2015


On Thursday, September 03, 2015 at 07:30:08 AM, Jaehoon Chung wrote:
> Hi,

Hi,

> On 09/03/2015 09:27 AM, Chin Liang See wrote:
> > On Wed, 2015-09-02 at 12:32 +0200, marex at denx.de wrote:
> [snip]

thanks

> >>>>> Would want to hear more from Jaehoon as Exynos and SOCFPGA are the
> >>>>> one setting up these values.
> >>>> 
> >>>> Since this approach is not based on dwmmc TRM, it's based on SOCFPGA
> >>>> SoC, i think that it doesn't need to include into dwmmc core.
> >>>> If need to located into dwmmc core, this code needs to modify more.
> >>>> 
> >>>> As drvsel and clksmpl are used at Exynos and SoCFPGA, it's not core
> >>>> feature. Other SoC can't be used them. we don't know.
> >>> 
> >>> Plus the way that this function is implemented, it is very specific to
> >>> SoCFGA, as the tables and rows are representing 45 degree increments
> >>> for the drvsel and smplsel value. Other platforms can have either more
> >>> or less granularity in the drvsel and smplsel values.
> >> 
> >> How is this SMPLSEL and DRVSEL implemented on Exynos ?
> 
> Exynos is using CLKSEL register in dw-mmc controller.
> It's exynos specific register in dwmmc controller. It's also represented 45
> degree increment. SELCK_DRV is bit[18:16] or more. SELCLK_SAMPLE is
> bit[2:0] or more. There are other bits relevant to tuning clock. '_more_'
> means that it can be changed bandwidth.
> 
> Anyway, I think there is no right method about finding the best smplclk and
> drvsel. If this is generic method, i will pick this. But i don't think so,
> and there is no benefit for exynos.
> 
> smplclk and drvsel value need to process the tuning sequence.
> There is no tuning case at bootloader, since it's not implemented about
> HS200 or upper mode.
> 
> Clksel an drvsel value are passed by device tree.

In that case, maybe SoCFPGA should also pick those values from DT ? It would
keep the code simple and in case there is a problematic board, it could use
u-boot application to perform the tuning.

Best regards,
Marek Vasut


More information about the U-Boot mailing list