[U-Boot] [PATCH v2 1/3] mx6: ddr: Adjust MDREF register settings for MX6UL
Fabio Estevam
festevam at gmail.com
Mon Aug 29 19:54:37 CEST 2016
From: Fabio Estevam <fabio.estevam at nxp.com>
When running a NXP 4.1 kernel with U-Boot mainline we observe a
hang when going into the lowest operational point of cpufreq.
After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting.
In all the DDR3 MX6UL boards we have the following configuration
for MDREF:
DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 -->Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes
So adjust the MDREF initialization for MX6UL to fix the kernel
hang issue.
Reported-by: Eric Nelson <eric at nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam at nxp.com>
---
Changes since v1:
- Newly introduced in this version
arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index f151eec..56d3e65 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
u32 val;
- u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+ u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
@@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
MMDC1(mpzqhwctrl, val);
/* Step 12: Configure and activate periodic refresh */
- mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
- (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
+ if (!is_mx6ul()) {
+ refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
+ refr = 7; /* REFR: Refresh Rate - 8 refreshes */
+ } else {
+ refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */
+ refr = 1; /* REFR: Refresh Rate - 2 refreshes */
+ }
+ mmdc0->mdref = (refsel << 14) | (refr << 11);
/* Step 13: Deassert config request - init complete */
mmdc0->mdscr = 0x00000000;
--
1.9.1
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