[U-Boot] [PATCH 2/7] net: stm32: add designware mac glue code for stm32
Michael Kurz
michi.kurz at gmail.com
Wed Nov 2 18:41:17 CET 2016
On Tue, 1 Nov 2016, Joe Hershberger wrote:
> On Tue, Nov 1, 2016 at 4:54 PM, Michael Kurz <michi.kurz at gmail.com> wrote:
>> This patch adds glue code required for enabling the designware
>> mac on stm32f7 devices.
>>
>> Signed-off-by: Michael Kurz <michi.kurz at gmail.com>
>> ---
>>
>> arch/arm/include/asm/arch-stm32f7/rcc.h | 8 ++++
>> arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 2 +
>> arch/arm/include/asm/arch-stm32f7/syscfg.h | 39 +++++++++++++++++
>> arch/arm/mach-stm32/stm32f7/clock.c | 9 ++++
>> board/st/stm32f746-disco/stm32f746-disco.c | 56 ++++++++++++++++++++++++
>> configs/stm32f746-disco_defconfig | 15 ++++++-
>> drivers/net/designware.c | 1 +
>> include/configs/stm32f746-disco.h | 9 +++-
>> 8 files changed, 136 insertions(+), 3 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-stm32f7/syscfg.h
>>
>> diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
>> index 8bfb7b6..03191a1 100644
>> --- a/arch/arm/include/asm/arch-stm32f7/rcc.h
>> +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
>> @@ -61,4 +61,12 @@
>> #define RCC_ENR_GPIO_J_EN (1 << 9)
>> #define RCC_ENR_GPIO_K_EN (1 << 10)
>
> Please use the BIT() macro throughout for these constants.
Will do and resubmit as v2.
>
>>
>> +/*
>> + * RCC STMMAC specific definitions
>> + */
>> +#define RCC_ENR_ETHMAC_EN (1 << 25)
>> +#define RCC_ENR_ETHMAC_TX_EN (1 << 26)
>> +#define RCC_ENR_ETHMAC_RX_EN (1 << 27)
>> +#define RCC_ENR_ETHMAC_PTP_EN (1 << 28)
>> +
>> #endif
>> diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
>> index 38adc4e..cc720be 100644
>> --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
>> +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
>> @@ -33,6 +33,8 @@ enum periph_clock {
>> GPIO_I_CLOCK_CFG,
>> GPIO_J_CLOCK_CFG,
>> GPIO_K_CLOCK_CFG,
>> + SYSCFG_CLOCK_CFG,
>> + STMMAC_CLOCK_CFG,
>> };
>>
>> #endif /* __ASM_ARM_ARCH_PERIPH_H */
>> diff --git a/arch/arm/include/asm/arch-stm32f7/syscfg.h b/arch/arm/include/asm/arch-stm32f7/syscfg.h
>> new file mode 100644
>> index 0000000..93cde22
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-stm32f7/syscfg.h
>> @@ -0,0 +1,39 @@
>> +/*
>> + * (C) Copyright 2016
>> + * Michael Kurz, michi.kurz at gmail.com.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef _STM32_SYSCFG_H
>> +#define _STM32_SYSCFG_H
>> +
>> +struct stm32_syscfg_regs {
>> + u32 memrmp;
>> + u32 pmc;
>> + u32 exticr1;
>> + u32 exticr2;
>> + u32 exticr3;
>> + u32 exticr4;
>> + u32 cmpcr;
>> +};
>> +
>> +/*
>> + * SYSCFG registers base
>> + */
>> +#define STM32_SYSCFG_BASE 0x40013800
>
> Maybe this should come from the config?
>
I'll move it to the config for now. Ideally this would come from the
device tree. But that's for a future patch.
>> +#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
>> +
>> +/* SYSCFG memory remap register */
>> +#define SYSCFG_MEMRMP_MEM_BOOT (1 << 0)
>> +#define SYSCFG_MEMRMP_SWP_FMC (1 << 10)
>> +
>> +/* SYSCFG peripheral mode configuration register */
>> +#define SYSCFG_PMC_ADCXDC2 (1 << 16)
>> +#define SYSCFG_PMC_MII_RMII_SEL (1 << 23)
>> +
>> +/* Compensation cell control register */
>> +#define SYSCFG_CMPCR_CMP_PD (1 << 0)
>> +#define SYSCFG_CMPCR_READY (1 << 8)
>> +
>> +#endif
>> diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
>> index 78d22d4..314be95 100644
>> --- a/arch/arm/mach-stm32/stm32f7/clock.c
>> +++ b/arch/arm/mach-stm32/stm32f7/clock.c
>> @@ -49,6 +49,7 @@
>> #define RCC_CFGR_PPRE2_SHIFT 13
>>
>> #define RCC_APB1ENR_PWREN (1 << 28)
>> +#define RCC_APB2ENR_SYSCFGEN (1 << 14)
>>
>> /*
>> * RCC USART specific definitions
>> @@ -278,6 +279,14 @@ void clock_setup(int peripheral)
>> case GPIO_K_CLOCK_CFG:
>> setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
>> break;
>> + case SYSCFG_CLOCK_CFG:
>> + setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_APB2ENR_SYSCFGEN);
>> + break;
>> + case STMMAC_CLOCK_CFG:
>> + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_ETHMAC_EN);
>> + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_ETHMAC_RX_EN);
>> + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_ETHMAC_TX_EN);
>> + break;
>> default:
>> break;
>> }
>> diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
>> index 404fdfa..3634b0e 100644
>> --- a/board/st/stm32f746-disco/stm32f746-disco.c
>> +++ b/board/st/stm32f746-disco/stm32f746-disco.c
>> @@ -16,6 +16,7 @@
>> #include <dm/platform_data/serial_stm32x7.h>
>> #include <asm/arch/stm32_periph.h>
>> #include <asm/arch/stm32_defs.h>
>> +#include <asm/arch/syscfg.h>
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -282,6 +283,55 @@ U_BOOT_DEVICE(stm32x7_serials) = {
>> .platdata = &serial_platdata,
>> };
>>
>> +#ifdef CONFIG_ETH_DESIGNWARE
>> +const struct stm32_gpio_ctl gpio_ctl_eth = {
>> + .mode = STM32_GPIO_MODE_AF,
>> + .otype = STM32_GPIO_OTYPE_PP,
>> + .speed = STM32_GPIO_SPEED_100M,
>> + .pupd = STM32_GPIO_PUPD_NO,
>> + .af = STM32_GPIO_AF11
>> +};
>> +
>> +static const struct stm32_gpio_dsc eth_gpio[] = {
>> + {STM32_GPIO_PORT_A, STM32_GPIO_PIN_1}, /* ETH_RMII_REF_CLK */
>> + {STM32_GPIO_PORT_A, STM32_GPIO_PIN_2}, /* ETH_MDIO */
>> + {STM32_GPIO_PORT_A, STM32_GPIO_PIN_7}, /* ETH_RMII_CRS_DV */
>> +
>> + {STM32_GPIO_PORT_C, STM32_GPIO_PIN_1}, /* ETH_MDC */
>> + {STM32_GPIO_PORT_C, STM32_GPIO_PIN_4}, /* ETH_RMII_RXD0 */
>> + {STM32_GPIO_PORT_C, STM32_GPIO_PIN_5}, /* ETH_RMII_RXD1 */
>> +
>> + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_11}, /* ETH_RMII_TX_EN */
>> + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_13}, /* ETH_RMII_TXD0 */
>> + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_14}, /* ETH_RMII_TXD1 */
>> +};
>> +
>> +static int stmmac_setup(void)
>> +{
>> + int res = 0;
>> + int i;
>> +
>> + clock_setup(SYSCFG_CLOCK_CFG);
>> +
>> + /* Set >RMII mode */
>> + STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
>> +
>> + clock_setup(GPIO_A_CLOCK_CFG);
>> + clock_setup(GPIO_C_CLOCK_CFG);
>> + clock_setup(GPIO_G_CLOCK_CFG);
>> +
>> + for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) {
>> + res = stm32_gpio_config(ð_gpio[i], &gpio_ctl_eth);
>> + if (res)
>> + return res;
>> + }
>> +
>> + clock_setup(STMMAC_CLOCK_CFG);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> u32 get_board_rev(void)
>> {
>> return 0;
>> @@ -296,6 +346,12 @@ int board_early_init_f(void)
>> if (res)
>> return res;
>>
>> +#ifdef CONFIG_ETH_DESIGNWARE
>> + res = stmmac_setup();
>> + if (res)
>> + return res;
>> +#endif
>> +
>> return 0;
>> }
>>
>> diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
>> index 7f6a442..7301380 100644
>> --- a/configs/stm32f746-disco_defconfig
>> +++ b/configs/stm32f746-disco_defconfig
>> @@ -12,7 +12,20 @@ CONFIG_AUTOBOOT_KEYED=y
>> CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
>> CONFIG_AUTOBOOT_STOP_STR=" "
>> # CONFIG_CMD_IMLS is not set
>> +# CONFIG_CMD_FPGA is not set
>> # CONFIG_CMD_SETEXPR is not set
>> +CONFIG_CMD_DHCP=y
>> +CONFIG_CMD_MII=y
>> +CONFIG_CMD_PING=y
>> +CONFIG_CMD_SNTP=y
>> +CONFIG_CMD_DNS=y
>> +CONFIG_CMD_LINK_LOCAL=y
>> CONFIG_CMD_TIMER=y
>> -CONFIG_OF_LIBFDT=y
>> +CONFIG_OF_CONTROL=y
>> +CONFIG_NET_RANDOM_ETHADDR=y
>> +CONFIG_NETCONSOLE=y
>> +CONFIG_DM_ETH=y
>> +CONFIG_ETH_DESIGNWARE=y
>> +# CONFIG_SPL_SERIAL_PRESENT is not set
>> +CONFIG_OF_LIBFDT_OVERLAY=y
>> # CONFIG_EFI_LOADER is not set
>> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
>> index 9e6d726..883ca5a 100644
>> --- a/drivers/net/designware.c
>> +++ b/drivers/net/designware.c
>> @@ -738,6 +738,7 @@ static const struct udevice_id designware_eth_ids[] = {
>> { .compatible = "allwinner,sun7i-a20-gmac" },
>> { .compatible = "altr,socfpga-stmmac" },
>> { .compatible = "amlogic,meson6-dwmac" },
>> + { .compatible = "st,stm32-dwmac" },
>> { }
>> };
>>
>> diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
>> index 4391bff..4088064 100644
>> --- a/include/configs/stm32f746-disco.h
>> +++ b/include/configs/stm32f746-disco.h
>> @@ -42,6 +42,11 @@
>> #define CONFIG_STM32_FLASH
>> #define CONFIG_STM32X7_SERIAL
>>
>> +#define CONFIG_DESIGNWARE_ETH
>> +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
>> +#define CONFIG_DW_ALTDESCRIPTOR
>> +#define CONFIG_MII
>> +
>> #define CONFIG_STM32_HSE_HZ 25000000
>> #define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
>> #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
>> @@ -56,8 +61,8 @@
>> + sizeof(CONFIG_SYS_PROMPT) + 16)
>>
>> #define CONFIG_SYS_MAXARGS 16
>> -#define CONFIG_SYS_MALLOC_LEN (16 * 1024)
>> -#define CONFIG_STACKSIZE (64 << 10)
>> +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
>> +#define CONFIG_STACKSIZE (256 * 1024)
>>
>> #define CONFIG_BAUDRATE 115200
>> #define CONFIG_BOOTARGS \
>> --
>> 2.1.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
More information about the U-Boot
mailing list