[U-Boot] [PATCH v2] gpio: dwapb: Add support for port B

[Marek Vasut]

On 11/03/2016 09:54 AM, Phil Edworthy wrote:
> The IP supports two ports, A and B, each providing up to 32 gpios.
> The driver already creates a 2nd gpio bank by reading the 2nd node
> from DT, so this is quite a simple change to support the 2nd bank.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
> ---
> v2:
>  Use an offset element in the platform data instead of if-elses.
> ---
>  drivers/gpio/dwapb_gpio.c | 25 ++++++++++++++++++-------
>  1 file changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
> index 471e18a..e7693a1 100644
> --- a/drivers/gpio/dwapb_gpio.c
> +++ b/drivers/gpio/dwapb_gpio.c
> @@ -21,6 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>  
>  #define GPIO_SWPORTA_DR		0x00
>  #define GPIO_SWPORTA_DDR	0x04
> +#define GPIO_SWPORTB_DR		0x0C
> +#define GPIO_SWPORTB_DDR	0x10

#define GPIO_SWPORT_DR(p)	((p) * 0xc)
#define GPIO_SWPORT_DDR(p)	(((p) * 0xc) + 0x4)

>  #define GPIO_INTEN		0x30
>  #define GPIO_INTMASK		0x34
>  #define GPIO_INTTYPE_LEVEL	0x38
> @@ -29,10 +31,12 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define GPIO_PORTA_DEBOUNCE	0x48
>  #define GPIO_PORTA_EOI		0x4c
>  #define GPIO_EXT_PORTA		0x50
> +#define GPIO_EXT_PORTB		0x54

#define GPIO_EXT_PORT(p) (0x50 + (p) * 4)

>  
>  struct gpio_dwapb_platdata {
>  	const char	*name;
>  	int		bank;
> +	int		offset;
>  	int		pins;
>  	fdt_addr_t	base;
>  };
> @@ -41,7 +45,8 @@ static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
>  {
>  	struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
>  
> -	clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
> +	clrbits_le32(plat->base + plat->offset + GPIO_SWPORTA_DDR, 1 << pin);
> +
>  	return 0;
>  }
>  
> @@ -50,12 +55,12 @@ static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
>  {
>  	struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
>  
> -	setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
> +	setbits_le32(plat->base + plat->offset + GPIO_SWPORTA_DDR, 1 << pin);
>  
>  	if (val)
> -		setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
> +		setbits_le32(plat->base + plat->offset + GPIO_SWPORTA_DR, 1 << pin);
>  	else
> -		clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
> +		clrbits_le32(plat->base + plat->offset + GPIO_SWPORTA_DR, 1 << pin);
>  
>  	return 0;
>  }
> @@ -63,7 +68,12 @@ static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
>  static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
>  {
>  	struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
> -	return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin));
> +
> +	/* Unfortunately, the offset for the EXT_PORTx register is different */
> +	if (plat->bank == 0)
> +		return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin));
> +	else
> +		return !!(readl(plat->base + GPIO_EXT_PORTB) & (1 << pin));

See above how to make this sane :)

>  }
>  
>  
> @@ -72,9 +82,9 @@ static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
>  	struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
>  
>  	if (val)
> -		setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
> +		setbits_le32(plat->base + plat->offset + GPIO_SWPORTA_DR, 1 << pin);
>  	else
> -		clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
> +		clrbits_le32(plat->base + plat->offset + GPIO_SWPORTA_DR, 1 << pin);
>  
>  	return 0;
>  }
> @@ -131,6 +141,7 @@ static int gpio_dwapb_bind(struct udevice *dev)
>  
>  		plat->base = base;
>  		plat->bank = bank;
> +		plat->offset = bank * 0xC;
>  		plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
>  		plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
>  						NULL);
> 


-- 
Best regards,
Marek Vasut