[U-Boot] [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related erratum

[york sun]

On 11/04/2016 04:18 AM, Shengzhou Liu wrote:
> - add additional function erratum_a009942_check_cpo to check if the
>   board needs tuning CPO calibration for optimal setting.
> - move ERRATUM_A009942(with revision to check cpo_sample option) from
>   fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
> - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
> - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Shengzhou,

There is an issue for moving the erratum 9942 workaround to ctrl_regs.c. 
This workaround requires setting debug register in a read-modify-write 
fashion. You won't be able to read the debug register in ctrl_regs.c file.

York