[U-Boot] [PATCH v2 2/7] ARM: stm32: cleanup stm32f7 files
Michael Kurz
michi.kurz at gmail.com
Fri Nov 4 20:21:07 CET 2016
Cleanup stm32f7 files:
- use BIT macro
- use GENMASK macro
- prefix all constants with STM32_
- remove double constants
Signed-off-by: Michael Kurz <michi.kurz at gmail.com>
---
Changes in v2:
- add cleanup patch
arch/arm/include/asm/arch-stm32f4/stm32.h | 2 +-
arch/arm/include/asm/arch-stm32f7/fmc.h | 7 +-
arch/arm/include/asm/arch-stm32f7/gpt.h | 9 +-
arch/arm/include/asm/arch-stm32f7/rcc.h | 64 -------
arch/arm/include/asm/arch-stm32f7/stm32.h | 119 +++++-------
arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 3 +
arch/arm/mach-stm32/stm32f7/clock.c | 227 ++++++++++++++---------
arch/arm/mach-stm32/stm32f7/timer.c | 4 +-
board/st/stm32f746-disco/stm32f746-disco.c | 10 +-
drivers/mtd/stm32_flash.c | 2 +-
drivers/serial/serial_stm32x7.c | 4 +-
11 files changed, 203 insertions(+), 248 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-stm32f7/rcc.h
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 6cc1966..b77345a 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -102,7 +102,7 @@ struct stm32_pwr_regs {
#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
-#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
+#define STM32_FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 16 * 1024,
diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h
index 7dd5077..24e6f1e 100644
--- a/arch/arm/include/asm/arch-stm32f7/fmc.h
+++ b/arch/arm/include/asm/arch-stm32f7/fmc.h
@@ -24,7 +24,6 @@ struct stm32_fmc_regs {
/*
* FMC registers base
*/
-#define STM32_SDRAM_FMC_BASE 0xA0000140
#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
/* Control register SDCR */
@@ -58,12 +57,12 @@ struct stm32_fmc_regs {
#define FMC_SDCMR_MODE_SELFREFRESH 5
#define FMC_SDCMR_MODE_POWERDOWN 6
-#define FMC_SDCMR_BANK_1 (1 << 4)
-#define FMC_SDCMR_BANK_2 (1 << 3)
+#define FMC_SDCMR_BANK_1 BIT(4)
+#define FMC_SDCMR_BANK_2 BIT(3)
#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-#define FMC_SDSR_BUSY (1 << 5)
+#define FMC_SDSR_BUSY BIT(5)
#define FMC_BUSY_WAIT() do { \
__asm__ __volatile__ ("dsb" : : : "memory"); \
diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h
index 903bdf6..7591519 100644
--- a/arch/arm/include/asm/arch-stm32f7/gpt.h
+++ b/arch/arm/include/asm/arch-stm32f7/gpt.h
@@ -34,12 +34,11 @@ struct gpt_regs {
u32 tim2_5_or;
};
-struct gpt_regs *const gpt1_regs_ptr =
- (struct gpt_regs *)TIM2_BASE;
+struct gpt_regs *const gpt1_regs_ptr = (struct gpt_regs *)STM32_TIM2_BASE;
/* Timer control1 register */
-#define GPT_CR1_CEN 0x0001
-#define GPT_MODE_AUTO_RELOAD (1 << 7)
+#define GPT_CR1_CEN BIT(0)
+#define GPT_MODE_AUTO_RELOAD BIT(7)
/* Auto reload register for free running config */
#define GPT_FREE_RUNNING 0xFFFFFFFF
@@ -48,6 +47,6 @@ struct gpt_regs *const gpt1_regs_ptr =
#define CONFIG_STM32_HZ 1000
/* Timer Event Generation registers */
-#define TIM_EGR_UG (1 << 0)
+#define TIM_EGR_UG BIT(0)
#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
deleted file mode 100644
index 8bfb7b6..0000000
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha at st.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _STM32_RCC_H
-#define _STM32_RCC_H
-
-#define RCC_CR 0x00 /* clock control */
-#define RCC_PLLCFGR 0x04 /* PLL configuration */
-#define RCC_CFGR 0x08 /* clock configuration */
-#define RCC_CIR 0x0C /* clock interrupt */
-#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */
-#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */
-#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */
-#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */
-#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */
-#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */
-#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */
-#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */
-#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */
-#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */
-#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */
-#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */
-#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */
-#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */
-#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */
-#define RCC_BDCR 0x70 /* Backup domain control */
-#define RCC_CSR 0x74 /* clock control & status */
-#define RCC_SSCGR 0x80 /* spread spectrum clock generation */
-#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */
-#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */
-#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */
-#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */
-
-#define RCC_APB1ENR_TIM2EN (1 << 0)
-#define RCC_APB1ENR_PWREN (1 << 28)
-
-/*
- * RCC USART specific definitions
- */
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
-
-/*
- * RCC GPIO specific definitions
- */
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index de55ae5..efc4fd7 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -9,46 +9,47 @@
#define _ASM_ARCH_HARDWARE_H
/* STM32F746 */
-#define ITCM_FLASH_BASE 0x00200000UL
-#define AXIM_FLASH_BASE 0x08000000UL
+#define STM32_ITCM_FLASH_BASE 0x00200000UL
+#define STM32_AXIM_FLASH_BASE 0x08000000UL
+
+#define STM32_ITCM_SRAM_BASE 0x00000000UL
+#define STM32_DTCM_SRAM_BASE 0x20000000UL
+#define STM32_SRAM1_BASE 0x20010000UL
+#define STM32_SRAM2_BASE 0x2004C000UL
+
+#define STM32_PERIPH_BASE 0x40000000UL
+
+#define STM32_APB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
+#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
+#define STM32_AHB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000)
+#define STM32_AHB3_PERIPH_BASE (STM32_PERIPH_BASE + 0x20000000)
+
+#define STM32_TIM2_BASE (STM32_APB1_PERIPH_BASE + 0x0000)
+#define STM32_USART2_BASE (STM32_APB1_PERIPH_BASE + 0x4400)
+#define STM32_USART3_BASE (STM32_APB1_PERIPH_BASE + 0x4800)
+#define STM32_PWR_BASE (STM32_APB1_PERIPH_BASE + 0x7000)
+
+#define STM32_USART1_BASE (STM32_APB2_PERIPH_BASE + 0x1000)
+#define STM32_USART6_BASE (STM32_APB2_PERIPH_BASE + 0x1400)
+#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800)
+
+#define STM32_GPIOA_BASE (STM32_AHB1_PERIPH_BASE + 0x0000)
+#define STM32_GPIOB_BASE (STM32_AHB1_PERIPH_BASE + 0x0400)
+#define STM32_GPIOC_BASE (STM32_AHB1_PERIPH_BASE + 0x0800)
+#define STM32_GPIOD_BASE (STM32_AHB1_PERIPH_BASE + 0x0C00)
+#define STM32_GPIOE_BASE (STM32_AHB1_PERIPH_BASE + 0x1000)
+#define STM32_GPIOF_BASE (STM32_AHB1_PERIPH_BASE + 0x1400)
+#define STM32_GPIOG_BASE (STM32_AHB1_PERIPH_BASE + 0x1800)
+#define STM32_GPIOH_BASE (STM32_AHB1_PERIPH_BASE + 0x1C00)
+#define STM32_GPIOI_BASE (STM32_AHB1_PERIPH_BASE + 0x2000)
+#define STM32_GPIOJ_BASE (STM32_AHB1_PERIPH_BASE + 0x2400)
+#define STM32_GPIOK_BASE (STM32_AHB1_PERIPH_BASE + 0x2800)
+#define STM32_RCC_BASE (STM32_AHB1_PERIPH_BASE + 0x3800)
+#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00)
+
+#define STM32_SDRAM_FMC_BASE (STM32_AHB3_PERIPH_BASE + 0x40000140)
-#define ITCM_SRAM_BASE 0x00000000UL
-#define DTCM_SRAM_BASE 0x20000000UL
-#define SRAM1_BASE 0x20010000UL
-#define SRAM2_BASE 0x2004C000UL
-
-#define PERIPH_BASE 0x40000000UL
-
-#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
-#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
-
-#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
-#define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
-#define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
-
-#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
-
-#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
-#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
-#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
-#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
-#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
-
-
-#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
@@ -62,43 +63,7 @@ enum clock {
CLOCK_APB1,
CLOCK_APB2
};
-#define STM32_BUS_MASK 0xFFFF0000
-
-struct stm32_rcc_regs {
- u32 cr; /* RCC clock control */
- u32 pllcfgr; /* RCC PLL configuration */
- u32 cfgr; /* RCC clock configuration */
- u32 cir; /* RCC clock interrupt */
- u32 ahb1rstr; /* RCC AHB1 peripheral reset */
- u32 ahb2rstr; /* RCC AHB2 peripheral reset */
- u32 ahb3rstr; /* RCC AHB3 peripheral reset */
- u32 rsv0;
- u32 apb1rstr; /* RCC APB1 peripheral reset */
- u32 apb2rstr; /* RCC APB2 peripheral reset */
- u32 rsv1[2];
- u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
- u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
- u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
- u32 rsv2;
- u32 apb1enr; /* RCC APB1 peripheral clock enable */
- u32 apb2enr; /* RCC APB2 peripheral clock enable */
- u32 rsv3[2];
- u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
- u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
- u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
- u32 rsv4;
- u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
- u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
- u32 rsv5[2];
- u32 bdcr; /* RCC Backup domain control */
- u32 csr; /* RCC clock control & status */
- u32 rsv6[2];
- u32 sscgr; /* RCC spread spectrum clock generation */
- u32 plli2scfgr; /* RCC PLLI2S configuration */
- u32 pllsaicfgr;
- u32 dckcfgr;
-};
-#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
+#define STM32_BUS_MASK GENMASK(31, 16)
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
@@ -106,7 +71,7 @@ struct stm32_pwr_regs {
u32 cr2; /* power control register 2 */
u32 csr2; /* power control/status register 2 */
};
-#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
+#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
int configure_clocks(void);
unsigned long clock_get(enum clock clck);
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
index 38adc4e..9b315a8 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -33,6 +33,9 @@ enum periph_clock {
GPIO_I_CLOCK_CFG,
GPIO_J_CLOCK_CFG,
GPIO_K_CLOCK_CFG,
+ SYSCFG_CLOCK_CFG,
+ TIMER2_CLOCK_CFG,
+ FMC_CLOCK_CFG,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
index 78d22d4..839d928 100644
--- a/arch/arm/mach-stm32/stm32f7/clock.c
+++ b/arch/arm/mach-stm32/stm32f7/clock.c
@@ -7,80 +7,130 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
-#define RCC_CR_HSION (1 << 0)
-#define RCC_CR_HSEON (1 << 16)
-#define RCC_CR_HSERDY (1 << 17)
-#define RCC_CR_HSEBYP (1 << 18)
-#define RCC_CR_CSSON (1 << 19)
-#define RCC_CR_PLLON (1 << 24)
-#define RCC_CR_PLLRDY (1 << 25)
+struct stm32_rcc_regs {
+ u32 cr; /* RCC clock control */
+ u32 pllcfgr; /* RCC PLL configuration */
+ u32 cfgr; /* RCC clock configuration */
+ u32 cir; /* RCC clock interrupt */
+ u32 ahb1rstr; /* RCC AHB1 peripheral reset */
+ u32 ahb2rstr; /* RCC AHB2 peripheral reset */
+ u32 ahb3rstr; /* RCC AHB3 peripheral reset */
+ u32 rsv0;
+ u32 apb1rstr; /* RCC APB1 peripheral reset */
+ u32 apb2rstr; /* RCC APB2 peripheral reset */
+ u32 rsv1[2];
+ u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
+ u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
+ u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
+ u32 rsv2;
+ u32 apb1enr; /* RCC APB1 peripheral clock enable */
+ u32 apb2enr; /* RCC APB2 peripheral clock enable */
+ u32 rsv3[2];
+ u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
+ u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
+ u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
+ u32 rsv4;
+ u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
+ u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
+ u32 rsv5[2];
+ u32 bdcr; /* RCC Backup domain control */
+ u32 csr; /* RCC clock control & status */
+ u32 rsv6[2];
+ u32 sscgr; /* RCC spread spectrum clock generation */
+ u32 plli2scfgr; /* RCC PLLI2S configuration */
+ u32 pllsaicfgr; /* PLLSAI configuration */
+ u32 dckcfgr1; /* dedicated clocks configuration register 1 */
+ u32 dckcfgr2; /* dedicated clocks configuration register 2 */
+};
+#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
-#define RCC_PLLCFGR_PLLM_MASK 0x3F
-#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK 0x30000
-#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
-#define RCC_PLLCFGR_PLLSRC (1 << 22)
-#define RCC_PLLCFGR_PLLM_SHIFT 0
-#define RCC_PLLCFGR_PLLN_SHIFT 6
-#define RCC_PLLCFGR_PLLP_SHIFT 16
-#define RCC_PLLCFGR_PLLQ_SHIFT 24
-#define RCC_CFGR_AHB_PSC_MASK 0xF0
-#define RCC_CFGR_APB1_PSC_MASK 0x1C00
-#define RCC_CFGR_APB2_PSC_MASK 0xE000
-#define RCC_CFGR_SW0 (1 << 0)
-#define RCC_CFGR_SW1 (1 << 1)
-#define RCC_CFGR_SW_MASK 0x3
-#define RCC_CFGR_SW_HSI 0
-#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
-#define RCC_CFGR_SWS0 (1 << 2)
-#define RCC_CFGR_SWS1 (1 << 3)
-#define RCC_CFGR_SWS_MASK 0xC
-#define RCC_CFGR_SWS_HSI 0
-#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT 4
-#define RCC_CFGR_PPRE1_SHIFT 10
-#define RCC_CFGR_PPRE2_SHIFT 13
+/*
+ * RCC AHB1ENR specific definitions
+ */
+#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
+#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
+#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
+#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
+#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
+#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
+#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
+#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
+#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
+#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
+#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
+#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
+#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
+#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
+#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
-#define RCC_APB1ENR_PWREN (1 << 28)
+/*
+ * RCC AHB3ENR specific definitions
+ */
+#define RCC_AHB3ENR_FMC_EN BIT(0)
/*
- * RCC USART specific definitions
+ * RCC APB1ENR specific definitions
*/
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
+#define RCC_APB1ENR_TIM2EN BIT(0)
+#define RCC_APB1ENR_USART2EN BIT(17)
+#define RCC_APB1ENR_USART3EN BIT(18)
+#define RCC_APB1ENR_PWREN BIT(28)
/*
- * Offsets of some PWR registers
+ * RCC APB2ENR specific definitions
*/
-#define PWR_CR1_ODEN (1 << 16)
-#define PWR_CR1_ODSWEN (1 << 17)
-#define PWR_CSR1_ODRDY (1 << 16)
-#define PWR_CSR1_ODSWRDY (1 << 17)
+#define RCC_APB2ENR_USART1EN BIT(4)
+#define RCC_APB2ENR_USART6EN BIT(5)
+#define RCC_APB2ENR_SYSCFGEN BIT(14)
+#define RCC_CR_HSION BIT(0)
+#define RCC_CR_HSEON BIT(16)
+#define RCC_CR_HSERDY BIT(17)
+#define RCC_CR_HSEBYP BIT(18)
+#define RCC_CR_CSSON BIT(19)
+#define RCC_CR_PLLON BIT(24)
+#define RCC_CR_PLLRDY BIT(25)
+
+#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
+#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
+#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
+#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
+#define RCC_PLLCFGR_PLLSRC BIT(22)
+#define RCC_PLLCFGR_PLLM_SHIFT 0
+#define RCC_PLLCFGR_PLLN_SHIFT 6
+#define RCC_PLLCFGR_PLLP_SHIFT 16
+#define RCC_PLLCFGR_PLLQ_SHIFT 24
+
+#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
+#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
+#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
+#define RCC_CFGR_SW0 BIT(0)
+#define RCC_CFGR_SW1 BIT(1)
+#define RCC_CFGR_SW_MASK GENMASK(1, 0)
+#define RCC_CFGR_SW_HSI 0
+#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
+#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
+#define RCC_CFGR_SWS0 BIT(2)
+#define RCC_CFGR_SWS1 BIT(3)
+#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
+#define RCC_CFGR_SWS_HSI 0
+#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT 4
+#define RCC_CFGR_PPRE1_SHIFT 10
+#define RCC_CFGR_PPRE2_SHIFT 13
/*
- * RCC GPIO specific definitions
+ * Offsets of some PWR registers
*/
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
struct pll_psc {
u8 pll_m;
@@ -92,21 +142,21 @@ struct pll_psc {
u8 apb2_psc;
};
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
+#define AHB_PSC_1 0
+#define AHB_PSC_2 0x8
+#define AHB_PSC_4 0x9
+#define AHB_PSC_8 0xA
+#define AHB_PSC_16 0xB
+#define AHB_PSC_64 0xC
+#define AHB_PSC_128 0xD
+#define AHB_PSC_256 0xE
+#define AHB_PSC_512 0xF
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
+#define APB_PSC_1 0
+#define APB_PSC_2 0x4
+#define APB_PSC_4 0x5
+#define APB_PSC_8 0x6
+#define APB_PSC_16 0x7
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
@@ -243,40 +293,49 @@ void clock_setup(int peripheral)
{
switch (peripheral) {
case USART1_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
+ setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
break;
case GPIO_A_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
break;
case GPIO_B_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
break;
case GPIO_C_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
break;
case GPIO_D_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
break;
case GPIO_E_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
break;
case GPIO_F_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
break;
case GPIO_G_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
break;
case GPIO_H_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
break;
case GPIO_I_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
break;
case GPIO_J_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
break;
case GPIO_K_CLOCK_CFG:
- setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
+ setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
+ break;
+ case SYSCFG_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
+ break;
+ case TIMER2_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
+ break;
+ case FMC_CLOCK_CFG:
+ setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
break;
default:
break;
diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c
index a7dee10..c15f8bb 100644
--- a/arch/arm/mach-stm32/stm32f7/timer.c
+++ b/arch/arm/mach-stm32/stm32f7/timer.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
+#include <asm/arch/stm32_defs.h>
#include <asm/arch/gpt.h>
-#include <asm/arch/rcc.h>
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ)
@@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
int timer_init(void)
{
/* Timer2 clock configuration */
- setbits_le32(RCC_BASE + RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
+ clock_setup(TIMER2_CLOCK_CFG);
/* Stop the timer */
writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 404fdfa..db5510e 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -10,7 +10,6 @@
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/rcc.h>
#include <asm/arch/fmc.h>
#include <dm/platdata.h>
#include <dm/platform_data/serial_stm32x7.h>
@@ -114,11 +113,6 @@ out:
return rv;
}
-/*
- * STM32 RCC FMC specific definitions
- */
-#define RCC_ENR_FMC (1 << 0) /* FMC module clock */
-
static inline u32 _ns2clk(u32 ns, u32 freq)
{
u32 tmp = freq/1000000;
@@ -176,7 +170,7 @@ int dram_init(void)
if (rv)
return rv;
- setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
+ clock_setup(FMC_CLOCK_CFG);
/*
* Get frequency for NS2CLK calculation.
@@ -273,7 +267,7 @@ out:
}
static const struct stm32x7_serial_platdata serial_platdata = {
- .base = (struct stm32_usart *)USART1_BASE,
+ .base = (struct stm32_usart *)STM32_USART1_BASE,
.clock = CONFIG_SYS_CLK_FREQ,
};
diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c
index e16b6cd..9e42c23 100644
--- a/drivers/mtd/stm32_flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -12,7 +12,7 @@
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE)
+#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_CNTL_BASE)
void stm32_flash_latency_cfg(int latency)
{
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 592c0bd..53a344e 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -21,9 +21,9 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
struct stm32_usart *const usart = plat->base;
u32 clock, int_div, frac_div, tmp;
- if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE)
+ if (((u32)usart & STM32_BUS_MASK) == STM32_APB1_PERIPH_BASE)
clock = clock_get(CLOCK_APB1);
- else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE)
+ else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2_PERIPH_BASE)
clock = clock_get(CLOCK_APB2);
else
return -EINVAL;
--
2.1.4
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