[U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

Wenbin Song wenbin.song at nxp.com
Wed Nov 16 10:23:34 CET 2016


Hi: york

Best Regards
Wenbin Song


> -----Original Message-----
> From: york sun
> Sent: Tuesday, November 15, 2016 5:24 AM
> To: Wenbin Song <wenbin.song at nxp.com>; albert.u.boot at aribaud.net;
> Mingkai Hu <mingkai.hu at nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 10/31/2016 08:35 PM, Wenbin song wrote:
> > The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> > alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> > is used to choose which offset will be used. If GIC_ADDR_BIT bit is
> > set, 4K alignment is used, or else 64K alignment is used. The rev1.0
> > silicon only supports the CIG offset with 4K alignment.
> 
> Wenbin,
> 
> According to your patch and your explanation, the rev 1 SoC supports 4K
> alignment only. The rev 1.1 and newer SoC supports both 4K and 64K. If you
> don't do anything in PBI, the default is 64K. 

[] yes. You are  correct .

Does this 64k alignment apply to
> any other SoCs?
> 
[]   This patch only apply  to ls1043a.  and the other SOCs  only support one kind of alignment style.  For example, ls1046a align with 64k, ls1012a align with 4k.
> York


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