[U-Boot] [PATCH 06/11] ARM: dts: dra7xx: sync DT with latest Linux
Lokesh Vutla
lokeshvutla at ti.com
Wed Nov 23 08:55:29 CET 2016
Sync all dra7xx based dts files with latest Linux
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
arch/arm/dts/dra7-dspeve-thermal.dtsi | 27 ++
arch/arm/dts/dra7-evm.dts | 507 +++++++++++++++++-------
arch/arm/dts/dra7-iva-thermal.dtsi | 27 ++
arch/arm/dts/dra7.dtsi | 717 +++++++++++++++++++++++++++-------
arch/arm/dts/dra72-evm-common.dtsi | 353 +++++++++--------
arch/arm/dts/dra72-evm-revc.dts | 30 +-
arch/arm/dts/dra72-evm-tps65917.dtsi | 134 +++++++
arch/arm/dts/dra72-evm.dts | 37 +-
arch/arm/dts/dra7xx-clocks.dtsi | 425 +++++++++++---------
include/dt-bindings/clk/ti-dra7-atl.h | 40 ++
include/dt-bindings/pinctrl/dra.h | 26 ++
11 files changed, 1683 insertions(+), 640 deletions(-)
create mode 100644 arch/arm/dts/dra7-dspeve-thermal.dtsi
create mode 100644 arch/arm/dts/dra7-iva-thermal.dtsi
create mode 100644 arch/arm/dts/dra72-evm-tps65917.dtsi
create mode 100644 include/dt-bindings/clk/ti-dra7-atl.h
diff --git a/arch/arm/dts/dra7-dspeve-thermal.dtsi b/arch/arm/dts/dra7-dspeve-thermal.dtsi
new file mode 100644
index 0000000..1c39a84
--- /dev/null
+++ b/arch/arm/dts/dra7-dspeve-thermal.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for DRA7x SoC DSPEVE thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+dspeve_thermal: dspeve_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 3>;
+
+ trips {
+ dspeve_crit: dspeve_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index be36d45..4d882ab 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -9,6 +9,8 @@
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/input/input.h>
/ {
model = "TI DRA742";
@@ -19,9 +21,9 @@
tick-timer = &timer2;
};
- memory {
+ memory at 0 {
device_type = "memory";
- reg = <0x80000000 0x60000000>; /* 1536 MB */
+ reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
evm_3v3_sd: fixedregulator-sd {
@@ -33,13 +35,23 @@
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
- mmc2_3v3: fixedregulator-mmc2 {
+ evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
- regulator-name = "mmc2_3v3";
+ regulator-name = "evm_3v3_sw";
+ vin-supply = <&sysen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
@@ -58,8 +70,89 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
+ vin-supply = <&sysen2>;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "dra7:usr1";
+ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led1 {
+ label = "dra7:usr2";
+ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "dra7:usr3";
+ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "dra7:usr4";
+ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ USER1 {
+ label = "btnUser1";
+ linux,code = <BTN_0>;
+ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
+ };
+
+ USER2 {
+ label = "btnUser2";
+ linux,code = <BTN_1>;
+ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&dra7_pmx_core {
@@ -68,163 +161,149 @@
vtt_pin: pinmux_vtt_pin {
pinctrl-single,pins = <
- 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
+ DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
- 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
- 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
+ DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
+ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
- 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+ DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
- 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
- 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
+ DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
+ DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
>;
};
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
- 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
- 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
- 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
- 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
- 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
- 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
+ DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
+ DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
+ DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
+ DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
+ DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
+ DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
>;
};
mcspi2_pins: pinmux_mcspi2_pins {
pinctrl-single,pins = <
- 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
- 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
+ DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
+ DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+ DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+ DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
- 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
- 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
- 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
- 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
+ DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
+ DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
- 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
- 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
- 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
- 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
- 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
- 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
- >;
- };
-
- qspi1_pins: pinmux_qspi1_pins {
- pinctrl-single,pins = <
- 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
- 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
- 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
- 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
- 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
- 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
- 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
- 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
- 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
- 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
+ DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
+ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
- 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+ DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
- 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+ DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
- * SW5.9 (GPMC_WPN) = LOW
- * SW5.1 (NAND_BOOTn) = HIGH */
+ * SW5.1 (NAND_BOOTn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
pinctrl-single,pins = <
- 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
- 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
- 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
+ DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
+ DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
+ DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
+ DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
+ DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
+ DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
+ DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
+ DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
+ DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
+ DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
+ DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
+ DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
+ DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
+ DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
+ DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
+ DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
+ DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
+ DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+ DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
+ DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+ DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+ DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
- 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
- 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
- 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
- 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
- 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
- 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
- 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
- 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
- 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
- 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
- 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
- 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
+ DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
+ DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
+ DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
+ DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
+ DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
/* Slave 2 */
- 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
+ DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
+ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
@@ -232,60 +311,85 @@
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
- 0x250 (MUX_MODE15)
- 0x254 (MUX_MODE15)
- 0x258 (MUX_MODE15)
- 0x25c (MUX_MODE15)
- 0x260 (MUX_MODE15)
- 0x264 (MUX_MODE15)
- 0x268 (MUX_MODE15)
- 0x26c (MUX_MODE15)
- 0x270 (MUX_MODE15)
- 0x274 (MUX_MODE15)
- 0x278 (MUX_MODE15)
- 0x27c (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
/* Slave 2 */
- 0x198 (MUX_MODE15)
- 0x19c (MUX_MODE15)
- 0x1a0 (MUX_MODE15)
- 0x1a4 (MUX_MODE15)
- 0x1a8 (MUX_MODE15)
- 0x1ac (MUX_MODE15)
- 0x1b0 (MUX_MODE15)
- 0x1b4 (MUX_MODE15)
- 0x1b8 (MUX_MODE15)
- 0x1bc (MUX_MODE15)
- 0x1c0 (MUX_MODE15)
- 0x1c4 (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
- 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
+ DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
- 0x23c (MUX_MODE15)
- 0x240 (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
- 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
- 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
- 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
- 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+
+ atl_pins: pinmux_atl_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
+ DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
+ >;
+ };
+
+ mcasp3_pins: pinmux_mcasp3_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
+ DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
+ DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
+ >;
+ };
+
+ mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
>;
};
};
@@ -317,7 +421,7 @@
/* VDD_DSPEVE */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1150000>;
+ regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
@@ -335,7 +439,7 @@
/* CORE_VDD */
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1060000>;
+ regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
@@ -363,6 +467,7 @@
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
regulator-boot-on;
};
@@ -392,6 +497,7 @@
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
+ regulator-allow-bypass;
};
ldoln_reg: ldoln {
@@ -410,12 +516,48 @@
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
+
+ /* REGEN1 is unused */
+
+ regen2: regen2 {
+ /* Needed for PMIC internal resources */
+ regulator-name = "regen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* REGEN3 is unused */
+
+ sysen1: sysen1 {
+ /* PMIC_REGEN_3V3 */
+ regulator-name = "sysen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sysen2: sysen2 {
+ /* PMIC_REGEN_DDR */
+ regulator-name = "sysen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
};
};
+ pcf_lcd: gpio at 20 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
pcf_gpio_21: gpio at 21 {
- compatible = "ti,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -427,6 +569,20 @@
u-boot,i2c-offset-len = <0>;
};
+ tlv320aic3106: tlv320aic3106 at 19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
};
&i2c2 {
@@ -434,6 +590,20 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
+
+ pcf_hdmi: gpio at 26 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ p1 {
+ /* vin6_sel_s0: high: VIN6, low: audio */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "vin6_sel_s0";
+ };
+ };
};
&i2c3 {
@@ -489,7 +659,7 @@
&mmc2 {
status = "okay";
- vmmc-supply = <&mmc2_3v3>;
+ vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
};
@@ -499,12 +669,10 @@
&qspi {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <76800000>;
m25p80 at 0 {
- compatible = "s25fl256s1","spi-flash";
+ compatible = "s25fl256s1", "spi-flash";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
@@ -588,9 +756,14 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
- ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand at 0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -613,7 +786,6 @@
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
@@ -710,3 +882,64 @@
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
+
+&atl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&atl_pins>;
+
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp3_pins>;
+ pinctrl-1 = <&mcasp3_sleep_pins>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/dra7-iva-thermal.dtsi b/arch/arm/dts/dra7-iva-thermal.dtsi
new file mode 100644
index 0000000..dd74a53
--- /dev/null
+++ b/arch/arm/dts/dra7-iva-thermal.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for DRA7x SoC IVA thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+iva_thermal: iva_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 4>;
+
+ trips {
+ iva_crit: iva_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 0f242e6..5570e30 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -10,13 +10,11 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
-#include "skeleton.dtsi"
-
#define MAX_SOURCES 400
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
@@ -57,10 +55,10 @@
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48211000 0x1000>,
- <0x48212000 0x1000>,
- <0x48214000 0x2000>,
- <0x48216000 0x2000>;
+ reg = <0x0 0x48211000 0x0 0x1000>,
+ <0x0 0x48212000 0x0 0x1000>,
+ <0x0 0x48214000 0x0 0x2000>,
+ <0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
@@ -69,10 +67,37 @@
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48281000 0x1000>;
+ reg = <0x0 0x48281000 0x0 0x1000>;
interrupt-parent = <&gic>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1176000 1160000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@@ -96,10 +121,10 @@
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x0 0x0 0xc0000000>;
ti,hwmods = "l3_main_1", "l3_main_2";
- reg = <0x44000000 0x1000000>,
- <0x45000000 0x1000>;
+ reg = <0x0 0x44000000 0x0 0x1000000>,
+ <0x0 0x45000000 0x0 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -117,13 +142,14 @@
ranges = <0 0x2000 0x2000>;
scm_conf: scm_conf at 0 {
- compatible = "syscon";
+ compatible = "syscon", "simple-bus";
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 0x0 0x1400>;
- pbias_regulator: pbias_regulator {
- compatible = "ti,pbias-omap";
+ pbias_regulator: pbias_regulator at e00 {
+ compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
@@ -142,7 +168,7 @@
dra7_pmx_core: pinmux at 1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
- reg = <0x1400 0x0464>;
+ reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
@@ -150,6 +176,34 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
+
+ scm_conf1: scm_conf at 1c04 {
+ compatible = "syscon";
+ reg = <0x1c04 0x0020>;
+ };
+
+ scm_conf_pcie: scm_conf at 1c24 {
+ compatible = "syscon";
+ reg = <0x1c24 0x0024>;
+ };
+
+ sdma_xbar: dma-router at b78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xb78 0xfc>;
+ #dma-cells = <1>;
+ dma-requests = <205>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&sdma>;
+ };
+
+ edma_xbar: dma-router at c78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xc78 0x7c>;
+ #dma-cells = <2>;
+ dma-requests = <204>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&edma>;
+ };
};
cm_core_aon: cm_core_aon at 5000 {
@@ -204,6 +258,11 @@
prm_clockdomains: clockdomains {
};
};
+
+ scm_wkup: scm_conf at c000 {
+ compatible = "syscon";
+ reg = <0xc000 0x1000>;
+ };
};
axi at 0 {
@@ -212,7 +271,7 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie at 51000000 {
+ pcie1: pcie at 51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -224,6 +283,7 @@
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ linux,pci-domain = <0>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
@@ -247,7 +307,7 @@
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
- pcie at 51000000 {
+ pcie at 51800000 {
compatible = "ti,dra7-pcie";
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -259,6 +319,7 @@
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ linux,pci-domain = <1>;
ti,hwmods = "pcie2";
phys = <&pcie2_phy>;
phy-names = "pcie-phy0";
@@ -275,6 +336,53 @@
};
};
+ ocmcram1: ocmcram at 40300000 {
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x80000>;
+ ranges = <0x0 0x40300000 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * This is a placeholder for an optional reserved
+ * region for use by secure software. The size
+ * of this region is not known until runtime so it
+ * is set as zero to either be updated to reserve
+ * space or left unchanged to leave all SRAM for use.
+ * On HS parts that that require the reserved region
+ * either the bootloader can update the size to
+ * the required amount or the node can be overridden
+ * from the board dts file for the secure platform.
+ */
+ sram-hs at 0 {
+ compatible = "ti,secure-ram";
+ reg = <0x0 0x0>;
+ };
+ };
+
+ /*
+ * NOTE: ocmcram2 and ocmcram3 are not available on all
+ * DRA7xx and AM57xx variants. Confirm availability in
+ * the data manual for the exact part number in use
+ * before enabling these nodes in the board dts file.
+ */
+ ocmcram2: ocmcram at 40400000 {
+ status = "disabled";
+ compatible = "mmio-sram";
+ reg = <0x40400000 0x100000>;
+ ranges = <0x0 0x40400000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ ocmcram3: ocmcram at 40500000 {
+ status = "disabled";
+ compatible = "mmio-sram";
+ reg = <0x40500000 0x100000>;
+ ranges = <0x0 0x40500000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
bandgap: bandgap at 4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
@@ -287,14 +395,9 @@
#thermal-sensor-cells = <1>;
};
- dra7_ctrl_core: ctrl_core at 4a002000 {
+ dsp1_system: dsp_system at 40d00000 {
compatible = "syscon";
- reg = <0x4a002000 0x6d0>;
- };
-
- dra7_ctrl_general: tisyscon at 4a002e00 {
- compatible = "syscon";
- reg = <0x4a002e00 0x7c>;
+ reg = <0x40d00000 0x100>;
};
sdma: dma-controller at 4a056000 {
@@ -309,6 +412,45 @@
dma-requests = <127>;
};
+ edma: edma at 43300000 {
+ compatible = "ti,edma3-tpcc";
+ ti,hwmods = "tpcc";
+ reg = <0x43300000 0x100000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <20 21>;
+ * for example. Note that these channels need to be
+ * masked in the xbar as well.
+ */
+ };
+
+ edma_tptc0: tptc at 43400000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc0";
+ reg = <0x43400000 0x100000>;
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
+
+ edma_tptc1: tptc at 43500000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc1";
+ reg = <0x43500000 0x100000>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
+
gpio1: gpio at 4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
@@ -398,79 +540,79 @@
};
uart1: serial at 4806a000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
reg-shift = <2>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 49>, <&sdma 50>;
+ dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
};
uart2: serial at 4806c000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 51>, <&sdma 52>;
+ dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
dma-names = "tx", "rx";
};
uart3: serial at 48020000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 53>, <&sdma 54>;
+ dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
dma-names = "tx", "rx";
};
uart4: serial at 4806e000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 55>, <&sdma 56>;
+ dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
dma-names = "tx", "rx";
};
uart5: serial at 48066000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 63>, <&sdma 64>;
+ dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
dma-names = "tx", "rx";
};
uart6: serial at 48068000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 79>, <&sdma 80>;
+ dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
dma-names = "tx", "rx";
};
uart7: serial at 48420000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
@@ -480,7 +622,7 @@
};
uart8: serial at 48422000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48422000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
@@ -490,7 +632,7 @@
};
uart9: serial at 48424000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48424000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
@@ -500,7 +642,7 @@
};
uart10: serial at 4ae2b000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@@ -768,12 +910,20 @@
ti,hwmods = "timer11";
};
+ timer12: timer at 4ae20000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae20000 0x80>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer12";
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
+
timer13: timer at 48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
- status = "disabled";
};
timer14: timer at 4882a000 {
@@ -781,7 +931,6 @@
reg = <0x4882a000 0x80>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer14";
- status = "disabled";
};
timer15: timer at 4882c000 {
@@ -789,7 +938,6 @@
reg = <0x4882c000 0x80>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer15";
- status = "disabled";
};
timer16: timer at 4882e000 {
@@ -797,7 +945,6 @@
reg = <0x4882e000 0x80>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer16";
- status = "disabled";
};
wdt2: wdt at 4ae14000 {
@@ -878,7 +1025,7 @@
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
- dmas = <&sdma 61>, <&sdma 62>;
+ dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
@@ -890,7 +1037,7 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
- dmas = <&sdma 47>, <&sdma 48>;
+ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -901,7 +1048,7 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
- dmas = <&sdma 77>, <&sdma 78>;
+ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -912,11 +1059,51 @@
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
- dmas = <&sdma 57>, <&sdma 58>;
+ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
};
+ mmu0_dsp1: mmu at 40d01000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x40d01000 0x100>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu0_dsp1";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ status = "disabled";
+ };
+
+ mmu1_dsp1: mmu at 40d02000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x40d02000 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu1_dsp1";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ status = "disabled";
+ };
+
+ mmu_ipu1: mmu at 58882000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x58882000 0x100>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu_ipu1";
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ status = "disabled";
+ };
+
+ mmu_ipu2: mmu at 55082000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x55082000 0x100>;
+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu_ipu2";
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ status = "disabled";
+ };
+
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";
@@ -1057,14 +1244,14 @@
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
+ dmas = <&sdma_xbar 35>,
+ <&sdma_xbar 36>,
+ <&sdma_xbar 37>,
+ <&sdma_xbar 38>,
+ <&sdma_xbar 39>,
+ <&sdma_xbar 40>,
+ <&sdma_xbar 41>,
+ <&sdma_xbar 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
status = "disabled";
@@ -1078,10 +1265,10 @@
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
+ dmas = <&sdma_xbar 43>,
+ <&sdma_xbar 44>,
+ <&sdma_xbar 45>,
+ <&sdma_xbar 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@@ -1094,7 +1281,7 @@
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
- dmas = <&sdma 15>, <&sdma 16>;
+ dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
dma-names = "tx0", "rx0";
status = "disabled";
};
@@ -1107,7 +1294,7 @@
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
+ dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
dma-names = "tx0", "rx0";
status = "disabled";
};
@@ -1115,10 +1302,9 @@
qspi: qspi at 4b300000 {
compatible = "ti,dra7xxx-qspi";
reg = <0x4b300000 0x100>,
- <0x5c000000 0x4000000>,
- <0x4a002558 0x4>;
- reg-names = "qspi_base", "qspi_mmap",
- "qspi_ctrlmod";
+ <0x5c000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ syscon-chipselects = <&scm_conf 0x558>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
@@ -1129,14 +1315,6 @@
status = "disabled";
};
- omap_control_sata: control-phy at 4a002374 {
- compatible = "ti,control-phy-pipe3";
- reg = <0x4a002374 0x4>;
- reg-names = "power";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- };
-
/* OCP2SCP3 */
ocp2scp at 4a090000 {
compatible = "ti,omap-ocp2scp";
@@ -1151,9 +1329,10 @@
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_sata>;
+ syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
};
@@ -1162,16 +1341,18 @@
reg = <0x4a094000 0x80>, /* phy_rx */
<0x4a094400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
- ctrl-module = <&omap_control_pcie1phy>;
+ syscon-phy-power = <&scm_conf_pcie 0x1c>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
- <&optfclk_pciephy_div>;
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
- "div-clk", "phy-div";
+ "div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
};
@@ -1180,16 +1361,18 @@
reg = <0x4a095000 0x80>, /* phy_rx */
<0x4a095400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
- ctrl-module = <&omap_control_pcie2phy>;
+ syscon-phy-power = <&scm_conf_pcie 0x20>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
- <&optfclk_pciephy_div>;
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
- "div-clk", "phy-div";
+ "div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
status = "disabled";
};
@@ -1205,23 +1388,6 @@
ti,hwmods = "sata";
};
- omap_control_pcie1phy: control-phy at 0x4a003c40 {
- compatible = "ti,control-phy-pcie";
- reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
- reg-names = "power", "control_sma", "pcie_pcs";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- };
-
- omap_control_pcie2phy: control-pcie at 0x4a003c44 {
- compatible = "ti,control-phy-pcie";
- reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
- reg-names = "power", "control_sma", "pcie_pcs";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- status = "disabled";
- };
-
rtc: rtc at 48838000 {
compatible = "ti,am3352-rtc";
reg = <0x48838000 0x100>;
@@ -1231,24 +1397,6 @@
clocks = <&sys_32k_ck>;
};
- omap_control_usb2phy1: control-phy at 4a002300 {
- compatible = "ti,control-phy-usb2";
- reg = <0x4a002300 0x4>;
- reg-names = "power";
- };
-
- omap_control_usb3phy1: control-phy at 4a002370 {
- compatible = "ti,control-phy-pipe3";
- reg = <0x4a002370 0x4>;
- reg-names = "power";
- };
-
- omap_control_usb2phy2: control-phy at 0x4a002e74 {
- compatible = "ti,control-phy-usb2-dra7";
- reg = <0x4a002e74 0x4>;
- reg-names = "power";
- };
-
/* OCP2SCP1 */
ocp2scp at 4a080000 {
compatible = "ti,omap-ocp2scp";
@@ -1259,9 +1407,9 @@
ti,hwmods = "ocp2scp1";
usb2_phy1: phy at 4a084000 {
- compatible = "ti,omap-usb2";
+ compatible = "ti,dra7x-usb2", "ti,omap-usb2";
reg = <0x4a084000 0x400>;
- ctrl-module = <&omap_control_usb2phy1>;
+ syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
@@ -1270,9 +1418,10 @@
};
usb2_phy2: phy at 4a085000 {
- compatible = "ti,omap-usb2";
+ compatible = "ti,dra7x-usb2-phy2",
+ "ti,omap-usb2";
reg = <0x4a085000 0x400>;
- ctrl-module = <&omap_control_usb2phy2>;
+ syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
clock-names = "wkupclk",
@@ -1286,7 +1435,7 @@
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_usb3phy1>;
+ syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
@@ -1309,10 +1458,14 @@
usb1: usb at 48890000 {
compatible = "snps,dwc3";
reg = <0x48890000 0x17000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
- tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
@@ -1332,10 +1485,14 @@
usb2: usb at 488d0000 {
compatible = "snps,dwc3";
reg = <0x488d0000 0x17000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
- tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
@@ -1357,8 +1514,12 @@
usb3: usb at 48910000 {
compatible = "snps,dwc3";
reg = <0x48910000 0x17000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- tx-fifo-resize;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
@@ -1379,10 +1540,16 @@
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 4 0>;
+ dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
status = "disabled";
};
@@ -1397,6 +1564,136 @@
status = "disabled";
};
+ mcasp1: mcasp at 48460000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp1";
+ reg = <0x48460000 0x2000>,
+ <0x45800000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
+ <&mcasp1_ahclkr_mux>;
+ clock-names = "fck", "ahclkx", "ahclkr";
+ status = "disabled";
+ };
+
+ mcasp2: mcasp at 48464000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp2";
+ reg = <0x48464000 0x2000>,
+ <0x45c00000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
+ <&mcasp2_ahclkr_mux>;
+ clock-names = "fck", "ahclkx", "ahclkr";
+ status = "disabled";
+ };
+
+ mcasp3: mcasp at 48468000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp3";
+ reg = <0x48468000 0x2000>,
+ <0x46000000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp4: mcasp at 4846c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp4";
+ reg = <0x4846c000 0x2000>,
+ <0x48436000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp5: mcasp at 48470000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp5";
+ reg = <0x48470000 0x2000>,
+ <0x4843a000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp6: mcasp at 48474000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp6";
+ reg = <0x48474000 0x2000>,
+ <0x4844c000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp7: mcasp at 48478000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp7";
+ reg = <0x48478000 0x2000>,
+ <0x48450000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp8: mcasp at 4847c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp8";
+ reg = <0x4847c000 0x2000>,
+ <0x48454000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
crossbar_mpu: crossbar at 4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
@@ -1412,25 +1709,34 @@
};
mac: ethernet at 48484000 {
- compatible = "ti,cpsw";
+ compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
- clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+ clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
- rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
+ cpts_clock_mult = <0x784CFE14>;
cpts_clock_shift = <29>;
syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
#size-cells = <1>;
+
+ /*
+ * Do not allow gating of cpsw clock as workaround
+ * for errata i877. Keeping internal clock disabled
+ * causes the device switching characteristics
+ * to degrade over time and eventually fail to meet
+ * the data manual delay time/skew specs.
+ */
+ ti,no-idle;
+
/*
* rx_thresh_pend
* rx_pend
@@ -1445,7 +1751,7 @@
status = "disabled";
davinci_mdio: mdio at 48485000 {
- compatible = "ti,davinci_mdio";
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
@@ -1527,12 +1833,157 @@
clock-names = "fck", "sys_clk";
};
};
+
+ epwmss0: epwmss at 4843e000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm0: pwm at 4843e200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: ecap at 4843e100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x4843e100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss at 48440000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm1: pwm at 48440200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap1: ecap at 48440100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48440100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss at 48442000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm2: pwm at 48442200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap2: ecap at 48442100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48442100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ aes1: aes at 4b500000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes1";
+ reg = <0x4b500000 0xa0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ aes2: aes at 4b700000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes2";
+ reg = <0x4b700000 0xa0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ des: des at 480a5000 {
+ compatible = "ti,omap4-des";
+ ti,hwmods = "des";
+ reg = <0x480a5000 0xa0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ sham: sham at 53100000 {
+ compatible = "ti,omap5-sham";
+ ti,hwmods = "sham";
+ reg = <0x4b101000 0x300>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 119 0>;
+ dma-names = "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ rng: rng at 48090000 {
+ compatible = "ti,omap4-rng";
+ ti,hwmods = "rng";
+ reg = <0x48090000 0x2000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
thermal_zones: thermal-zones {
#include "omap4-cpu-thermal.dtsi"
#include "omap5-gpu-thermal.dtsi"
#include "omap5-core-thermal.dtsi"
+ #include "dra7-dspeve-thermal.dtsi"
+ #include "dra7-iva-thermal.dtsi"
};
};
diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi
index 1e1ca72..c83f87f 100644
--- a/arch/arm/dts/dra72-evm-common.dtsi
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -9,24 +9,82 @@
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+ aliases {
+ display0 = &hdmi0;
+ };
+
chosen {
stdout-path = &uart1;
tick-timer = &timer2;
};
- aliases {
- display0 = &hdmi0;
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_5v0: fixedregulator-evm5v0 {
+ /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
};
- evm_3v3: fixedregulator-evm_3v3 {
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_3v3_sw: fixedregulator-evm_3v3 {
+ /* TPS22965DSG */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ evm_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_3v3_sw>;
+ enable-active-high;
+ gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_usb1 {
@@ -80,46 +138,81 @@
};
};
};
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
};
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
- 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
- 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
- 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
- 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
- 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
- 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
};
@@ -128,123 +221,31 @@
status = "okay";
clock-frequency = <400000>;
- tps65917: tps65917 at 58 {
- compatible = "ti,tps65917";
- reg = <0x58>;
-
- interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
- interrupt-controller;
- #interrupt-cells = <2>;
-
- ti,system-power-controller;
-
- tps65917_pmic {
- compatible = "ti,tps65917-pmic";
-
- tps65917_regulators: regulators {
- smps1_reg: smps1 {
- /* VDD_MPU */
- regulator-name = "smps1";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps2_reg: smps2 {
- /* VDD_CORE */
- regulator-name = "smps2";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1060000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_GPU IVA DSPEVE */
- regulator-name = "smps3";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps4_reg: smps4 {
- /* VDDS1V8 */
- regulator-name = "smps4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps5_reg: smps5 {
- /* VDD_DDR */
- regulator-name = "smps5";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /* LDO1_OUT --> SDIO */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-allow-bypass;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PLL */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4_reg: ldo4 {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
- };
- };
-
- tps65917_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps65917>;
- interrupts = <1 IRQ_TYPE_NONE>;
- wakeup-source;
- ti,palmas-long-press-seconds = <6>;
- };
- };
-
pcf_gpio_21: gpio at 21 {
- compatible = "ti,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
u-boot,i2c-offset-len = <0>;
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ tlv320aic3106: tlv320aic3106 at 19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
};
&i2c5 {
@@ -252,7 +253,7 @@
clock-frequency = <400000>;
pcf_hdmi: pcf8575 at 26 {
- compatible = "nxp,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
u-boot,i2c-offset-len = <0>;
reg = <0x26>;
gpio-controller;
@@ -286,12 +287,7 @@
};
&gpmc {
- /*
- * For the existing IOdelay configuration via U-Boot we don't
- * support NAND on dra72-evm. Keep it disabled. Enabling it
- * requires a different configuration by U-Boot.
- */
- status = "disabled";
+ status = "okay";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand at 0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
@@ -299,11 +295,11 @@
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* device IO registers */
+ reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
@@ -326,7 +322,6 @@
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
@@ -377,14 +372,6 @@
};
};
-&usb2_phy1 {
- phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldo4_reg>;
-};
-
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
@@ -394,7 +381,7 @@
};
&usb1 {
- dr_mode = "otg";
+ dr_mode = "peripheral";
};
&usb2 {
@@ -405,7 +392,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
- vmmc_aux-supply = <&ldo1_reg>;
+ vmmc-supply = <&evm_3v3_sd>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
@@ -421,7 +408,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
- vmmc-supply = <&evm_3v3>;
+ vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
@@ -433,6 +420,10 @@
&dcan1 {
status = "ok";
+ pinctrl-names = "default", "sleep", "active";
+ pinctrl-0 = <&dcan1_pins_sleep>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+ pinctrl-2 = <&dcan1_pins_default>;
};
&qspi {
@@ -498,8 +489,6 @@
&dss {
status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
@@ -511,3 +500,55 @@
};
};
};
+
+&atl {
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts
index 0f8a7ef..5a1bb34 100644
--- a/arch/arm/dts/dra72-evm-revc.dts
+++ b/arch/arm/dts/dra72-evm-revc.dts
@@ -11,25 +11,35 @@
/ {
model = "TI DRA722 Rev C EVM";
- memory {
+ memory at 0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
};
-&tps65917_regulators {
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> VDDA_1V8_PHY2 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
+&i2c1 {
+ tps65917: tps65917 at 58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
};
};
+#include "dra72-evm-tps65917.dtsi"
+
+&ldo2_reg {
+ /* LDO2_OUT --> VDDA_1V8_PHY2 */
+ regulator-always-on;
+ regulator-boot-on;
+};
+
&hdmi {
- vdda_video-supply = <&ldo2_reg>;
+ vdda-supply = <&ldo2_reg>;
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};
&mac {
diff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi
new file mode 100644
index 0000000..ee6dac4
--- /dev/null
+++ b/arch/arm/dts/dra72-evm-tps65917.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ */
+
+&tps65917 {
+ compatible = "ti,tps65917";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps1-in-supply = <&vsys_3v3>;
+ smps2-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_3v3>;
+ ldo4-in-supply = <&evm_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+};
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index f81f918..cd9c4ff 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -1,38 +1,45 @@
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <dra72-evm-common.dtsi>
-
+#include "dra72-evm-common.dtsi"
/ {
model = "TI DRA722";
- compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
- memory {
+ memory at 0 {
device_type = "memory";
- reg = <0x80000000 0x40000000>; /* 1024 MB */
+ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
};
+&i2c1 {
+ tps65917: tps65917 at 58 {
+ reg = <0x58>;
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <3>;
- phy-mode = "rgmii";
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ };
};
-&dss {
- status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
-};
+#include "dra72-evm-tps65917.dtsi"
&hdmi {
vdda-supply = <&ldo3_reg>;
};
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+};
+
&mac {
- mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
+ slaves = <1>;
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
};
diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
index 357bede..3330738 100644
--- a/arch/arm/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
clock-frequency = <32768>;
};
- sys_32k_ck: sys_32k_ck {
+ sys_clk32_crystal_ck: sys_clk32_crystal_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
+ sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <610>;
+ };
+
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -188,7 +196,7 @@
clock-frequency = <0>;
};
- dpll_abe_ck: dpll_abe_ck {
+ dpll_abe_ck: dpll_abe_ck at 1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -201,7 +209,7 @@
clocks = <&dpll_abe_ck>;
};
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
@@ -212,7 +220,7 @@
ti,invert-autoidle-bit;
};
- abe_clk: abe_clk {
+ abe_clk: abe_clk at 108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
@@ -221,7 +229,7 @@
ti,index-power-of-two;
};
- dpll_abe_m2_ck: dpll_abe_m2_ck {
+ dpll_abe_m2_ck: dpll_abe_m2_ck at 1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
@@ -232,7 +240,7 @@
ti,invert-autoidle-bit;
};
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
@@ -243,7 +251,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: dpll_core_byp_mux {
+ dpll_core_byp_mux: dpll_core_byp_mux at 12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -251,7 +259,7 @@
reg = <0x012c>;
};
- dpll_core_ck: dpll_core_ck {
+ dpll_core_ck: dpll_core_ck at 120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
@@ -264,7 +272,7 @@
clocks = <&dpll_core_ck>;
};
- dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck at 13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -283,14 +291,14 @@
clock-div = <1>;
};
- dpll_mpu_ck: dpll_mpu_ck {
+ dpll_mpu_ck: dpll_mpu_ck at 160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck at 170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
@@ -317,7 +325,7 @@
clock-div = <1>;
};
- dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+ dpll_dsp_byp_mux: dpll_dsp_byp_mux at 240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -325,14 +333,14 @@
reg = <0x0240>;
};
- dpll_dsp_ck: dpll_dsp_ck {
+ dpll_dsp_ck: dpll_dsp_ck at 234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
};
- dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+ dpll_dsp_m2_ck: dpll_dsp_m2_ck at 244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_ck>;
@@ -351,7 +359,7 @@
clock-div = <1>;
};
- dpll_iva_byp_mux: dpll_iva_byp_mux {
+ dpll_iva_byp_mux: dpll_iva_byp_mux at 1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -359,14 +367,14 @@
reg = <0x01ac>;
};
- dpll_iva_ck: dpll_iva_ck {
+ dpll_iva_ck: dpll_iva_ck at 1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
};
- dpll_iva_m2_ck: dpll_iva_m2_ck {
+ dpll_iva_m2_ck: dpll_iva_m2_ck at 1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_ck>;
@@ -385,7 +393,7 @@
clock-div = <1>;
};
- dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+ dpll_gpu_byp_mux: dpll_gpu_byp_mux at 2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -393,14 +401,14 @@
reg = <0x02e4>;
};
- dpll_gpu_ck: dpll_gpu_ck {
+ dpll_gpu_ck: dpll_gpu_ck at 2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
};
- dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+ dpll_gpu_m2_ck: dpll_gpu_m2_ck at 2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_ck>;
@@ -411,7 +419,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_m2_ck: dpll_core_m2_ck {
+ dpll_core_m2_ck: dpll_core_m2_ck at 130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
@@ -430,7 +438,7 @@
clock-div = <1>;
};
- dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+ dpll_ddr_byp_mux: dpll_ddr_byp_mux at 21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -438,14 +446,14 @@
reg = <0x021c>;
};
- dpll_ddr_ck: dpll_ddr_ck {
+ dpll_ddr_ck: dpll_ddr_ck at 210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+ dpll_ddr_m2_ck: dpll_ddr_m2_ck at 220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
@@ -456,7 +464,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+ dpll_gmac_byp_mux: dpll_gmac_byp_mux at 2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -464,14 +472,14 @@
reg = <0x02b4>;
};
- dpll_gmac_ck: dpll_gmac_ck {
+ dpll_gmac_ck: dpll_gmac_ck at 2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
- dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+ dpll_gmac_m2_ck: dpll_gmac_m2_ck at 2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
@@ -530,7 +538,7 @@
clock-div = <1>;
};
- dpll_eve_byp_mux: dpll_eve_byp_mux {
+ dpll_eve_byp_mux: dpll_eve_byp_mux at 290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -538,14 +546,14 @@
reg = <0x0290>;
};
- dpll_eve_ck: dpll_eve_ck {
+ dpll_eve_ck: dpll_eve_ck at 284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
- dpll_eve_m2_ck: dpll_eve_m2_ck {
+ dpll_eve_m2_ck: dpll_eve_m2_ck at 294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_eve_ck>;
@@ -564,7 +572,7 @@
clock-div = <1>;
};
- dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck at 140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -575,7 +583,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck at 144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -586,7 +594,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck at 154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -597,7 +605,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck at 158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -608,7 +616,7 @@
ti,invert-autoidle-bit;
};
- dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck at 15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@@ -625,7 +633,7 @@
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+ dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck at 228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
@@ -642,7 +650,7 @@
clocks = <&dpll_dsp_ck>;
};
- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+ dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck at 248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_x2_ck>;
@@ -659,7 +667,7 @@
clocks = <&dpll_gmac_ck>;
};
- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+ dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck at 2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -670,7 +678,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+ dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck at 2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -681,7 +689,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+ dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck at 2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +700,7 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+ dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck at 2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
@@ -727,7 +735,7 @@
clock-div = <1>;
};
- l3_iclk_div: l3_iclk_div {
+ l3_iclk_div: l3_iclk_div at 100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
@@ -777,7 +785,7 @@
clock-div = <1>;
};
- ipu1_gfclk_mux: ipu1_gfclk_mux {
+ ipu1_gfclk_mux: ipu1_gfclk_mux at 520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
@@ -785,7 +793,7 @@
reg = <0x0520>;
};
- mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+ mcasp1_ahclkr_mux: mcasp1_ahclkr_mux at 550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -793,7 +801,7 @@
reg = <0x0550>;
};
- mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+ mcasp1_ahclkx_mux: mcasp1_ahclkx_mux at 550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -801,7 +809,7 @@
reg = <0x0550>;
};
- mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+ mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux at 550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -809,7 +817,7 @@
reg = <0x0550>;
};
- timer5_gfclk_mux: timer5_gfclk_mux {
+ timer5_gfclk_mux: timer5_gfclk_mux at 558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -817,7 +825,7 @@
reg = <0x0558>;
};
- timer6_gfclk_mux: timer6_gfclk_mux {
+ timer6_gfclk_mux: timer6_gfclk_mux at 560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -825,7 +833,7 @@
reg = <0x0560>;
};
- timer7_gfclk_mux: timer7_gfclk_mux {
+ timer7_gfclk_mux: timer7_gfclk_mux at 568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -833,7 +841,7 @@
reg = <0x0568>;
};
- timer8_gfclk_mux: timer8_gfclk_mux {
+ timer8_gfclk_mux: timer8_gfclk_mux at 570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -841,7 +849,7 @@
reg = <0x0570>;
};
- uart6_gfclk_mux: uart6_gfclk_mux {
+ uart6_gfclk_mux: uart6_gfclk_mux at 580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -856,7 +864,7 @@
};
};
&prm_clocks {
- sys_clkin1: sys_clkin1 {
+ sys_clkin1: sys_clkin1 at 110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -864,28 +872,28 @@
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+ abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux at 118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
- abe_dpll_clk_mux: abe_dpll_clk_mux {
+ abe_dpll_clk_mux: abe_dpll_clk_mux at 10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
- abe_24m_fclk: abe_24m_fclk {
+ abe_24m_fclk: abe_24m_fclk at 11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
@@ -893,7 +901,7 @@
ti,dividers = <8>, <16>;
};
- aess_fclk: aess_fclk {
+ aess_fclk: aess_fclk at 178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
@@ -901,7 +909,7 @@
ti,max-div = <2>;
};
- abe_giclk_div: abe_giclk_div {
+ abe_giclk_div: abe_giclk_div at 174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
@@ -909,7 +917,7 @@
ti,max-div = <2>;
};
- abe_lp_clk_div: abe_lp_clk_div {
+ abe_lp_clk_div: abe_lp_clk_div at 1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +925,7 @@
ti,dividers = <16>, <32>;
};
- abe_sys_clk_div: abe_sys_clk_div {
+ abe_sys_clk_div: abe_sys_clk_div at 120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -925,14 +933,14 @@
ti,max-div = <2>;
};
- adc_gfclk_mux: adc_gfclk_mux {
+ adc_gfclk_mux: adc_gfclk_mux at 1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
- sys_clk1_dclk_div: sys_clk1_dclk_div {
+ sys_clk1_dclk_div: sys_clk1_dclk_div at 1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -941,7 +949,7 @@
ti,index-power-of-two;
};
- sys_clk2_dclk_div: sys_clk2_dclk_div {
+ sys_clk2_dclk_div: sys_clk2_dclk_div at 1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin2>;
@@ -950,7 +958,7 @@
ti,index-power-of-two;
};
- per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+ per_abe_x1_dclk_div: per_abe_x1_dclk_div at 1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
@@ -959,7 +967,7 @@
ti,index-power-of-two;
};
- dsp_gclk_div: dsp_gclk_div {
+ dsp_gclk_div: dsp_gclk_div at 18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_m2_ck>;
@@ -968,7 +976,7 @@
ti,index-power-of-two;
};
- gpu_dclk: gpu_dclk {
+ gpu_dclk: gpu_dclk at 1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_m2_ck>;
@@ -977,7 +985,7 @@
ti,index-power-of-two;
};
- emif_phy_dclk_div: emif_phy_dclk_div {
+ emif_phy_dclk_div: emif_phy_dclk_div at 190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_m2_ck>;
@@ -986,7 +994,7 @@
ti,index-power-of-two;
};
- gmac_250m_dclk_div: gmac_250m_dclk_div {
+ gmac_250m_dclk_div: gmac_250m_dclk_div at 19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
@@ -995,7 +1003,15 @@
ti,index-power-of-two;
};
- l3init_480m_dclk_div: l3init_480m_dclk_div {
+ gmac_main_clk: gmac_main_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&gmac_250m_dclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_480m_dclk_div: l3init_480m_dclk_div at 1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
@@ -1004,7 +1020,7 @@
ti,index-power-of-two;
};
- usb_otg_dclk_div: usb_otg_dclk_div {
+ usb_otg_dclk_div: usb_otg_dclk_div at 184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&usb_otg_clkin_ck>;
@@ -1013,7 +1029,7 @@
ti,index-power-of-two;
};
- sata_dclk_div: sata_dclk_div {
+ sata_dclk_div: sata_dclk_div at 1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -1022,7 +1038,7 @@
ti,index-power-of-two;
};
- pcie2_dclk_div: pcie2_dclk_div {
+ pcie2_dclk_div: pcie2_dclk_div at 1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1031,7 +1047,7 @@
ti,index-power-of-two;
};
- pcie_dclk_div: pcie_dclk_div {
+ pcie_dclk_div: pcie_dclk_div at 1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&apll_pcie_m2_ck>;
@@ -1040,7 +1056,7 @@
ti,index-power-of-two;
};
- emu_dclk_div: emu_dclk_div {
+ emu_dclk_div: emu_dclk_div at 194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -1049,7 +1065,7 @@
ti,index-power-of-two;
};
- secure_32k_dclk_div: secure_32k_dclk_div {
+ secure_32k_dclk_div: secure_32k_dclk_div at 1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&secure_32k_clk_src_ck>;
@@ -1058,21 +1074,21 @@
ti,index-power-of-two;
};
- clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+ clkoutmux0_clk_mux: clkoutmux0_clk_mux at 158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
- clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+ clkoutmux1_clk_mux: clkoutmux1_clk_mux at 15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
- clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+ clkoutmux2_clk_mux: clkoutmux2_clk_mux at 160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
@@ -1087,21 +1103,21 @@
clock-div = <2>;
};
- eve_clk: eve_clk {
+ eve_clk: eve_clk at 180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+ hdmi_dpll_clk_mux: hdmi_dpll_clk_mux at 164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
- mlb_clk: mlb_clk {
+ mlb_clk: mlb_clk at 134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlb_clkin_ck>;
@@ -1110,7 +1126,7 @@
ti,index-power-of-two;
};
- mlbp_clk: mlbp_clk {
+ mlbp_clk: mlbp_clk at 130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlbp_clkin_ck>;
@@ -1119,7 +1135,7 @@
ti,index-power-of-two;
};
- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+ per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div at 138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
@@ -1128,7 +1144,7 @@
ti,index-power-of-two;
};
- timer_sys_clk_div: timer_sys_clk_div {
+ timer_sys_clk_div: timer_sys_clk_div at 144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
@@ -1136,28 +1152,28 @@
ti,max-div = <2>;
};
- video1_dpll_clk_mux: video1_dpll_clk_mux {
+ video1_dpll_clk_mux: video1_dpll_clk_mux at 168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
- video2_dpll_clk_mux: video2_dpll_clk_mux {
+ video2_dpll_clk_mux: video2_dpll_clk_mux at 16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
- wkupaon_iclk_mux: wkupaon_iclk_mux {
+ wkupaon_iclk_mux: wkupaon_iclk_mux at 108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
- gpio1_dbclk: gpio1_dbclk {
+ gpio1_dbclk: gpio1_dbclk at 1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1165,7 +1181,7 @@
reg = <0x1838>;
};
- dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+ dcan1_sys_clk_mux: dcan1_sys_clk_mux at 1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
@@ -1173,7 +1189,7 @@
reg = <0x1888>;
};
- timer1_gfclk_mux: timer1_gfclk_mux {
+ timer1_gfclk_mux: timer1_gfclk_mux at 1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1181,7 +1197,7 @@
reg = <0x1840>;
};
- uart10_gfclk_mux: uart10_gfclk_mux {
+ uart10_gfclk_mux: uart10_gfclk_mux at 1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1190,14 +1206,14 @@
};
};
&cm_core_clocks {
- dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+ dpll_pcie_ref_ck: dpll_pcie_ref_ck at 200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
@@ -1216,7 +1232,7 @@
ti,bit-shift = <7>;
};
- apll_pcie_ck: apll_pcie_ck {
+ apll_pcie_ck: apll_pcie_ck at 21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1305,7 +1321,7 @@
clock-div = <1>;
};
- dpll_per_byp_mux: dpll_per_byp_mux {
+ dpll_per_byp_mux: dpll_per_byp_mux at 14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1313,14 +1329,14 @@
reg = <0x014c>;
};
- dpll_per_ck: dpll_per_ck {
+ dpll_per_ck: dpll_per_ck at 140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: dpll_per_m2_ck {
+ dpll_per_m2_ck: dpll_per_m2_ck at 150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
@@ -1339,7 +1355,7 @@
clock-div = <1>;
};
- dpll_usb_byp_mux: dpll_usb_byp_mux {
+ dpll_usb_byp_mux: dpll_usb_byp_mux at 18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1347,14 +1363,14 @@
reg = <0x018c>;
};
- dpll_usb_ck: dpll_usb_ck {
+ dpll_usb_ck: dpll_usb_ck at 180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
- dpll_usb_m2_ck: dpll_usb_m2_ck {
+ dpll_usb_m2_ck: dpll_usb_m2_ck at 190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
@@ -1365,7 +1381,7 @@
ti,invert-autoidle-bit;
};
- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+ dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck at 210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
@@ -1382,7 +1398,7 @@
clocks = <&dpll_per_ck>;
};
- dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck at 158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1393,7 +1409,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck at 15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1404,7 +1420,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+ dpll_per_h13x2_ck: dpll_per_h13x2_ck at 160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1415,7 +1431,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck at 164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1426,7 +1442,7 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck at 150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
@@ -1485,7 +1501,7 @@
clock-div = <2>;
};
- l3init_60m_fclk: l3init_60m_fclk {
+ l3init_60m_fclk: l3init_60m_fclk at 104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
@@ -1493,7 +1509,7 @@
ti,dividers = <1>, <8>;
};
- clkout2_clk: clkout2_clk {
+ clkout2_clk: clkout2_clk at 6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkoutmux2_clk_mux>;
@@ -1501,7 +1517,7 @@
reg = <0x06b0>;
};
- l3init_960m_gfclk: l3init_960m_gfclk {
+ l3init_960m_gfclk: l3init_960m_gfclk at 6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
@@ -1509,7 +1525,7 @@
reg = <0x06c0>;
};
- dss_32khz_clk: dss_32khz_clk {
+ dss_32khz_clk: dss_32khz_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1517,7 +1533,7 @@
reg = <0x1120>;
};
- dss_48mhz_clk: dss_48mhz_clk {
+ dss_48mhz_clk: dss_48mhz_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
@@ -1525,7 +1541,7 @@
reg = <0x1120>;
};
- dss_dss_clk: dss_dss_clk {
+ dss_dss_clk: dss_dss_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
@@ -1534,7 +1550,7 @@
ti,set-rate-parent;
};
- dss_hdmi_clk: dss_hdmi_clk {
+ dss_hdmi_clk: dss_hdmi_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
@@ -1542,7 +1558,7 @@
reg = <0x1120>;
};
- dss_video1_clk: dss_video1_clk {
+ dss_video1_clk: dss_video1_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
@@ -1550,7 +1566,7 @@
reg = <0x1120>;
};
- dss_video2_clk: dss_video2_clk {
+ dss_video2_clk: dss_video2_clk at 1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
@@ -1558,7 +1574,7 @@
reg = <0x1120>;
};
- gpio2_dbclk: gpio2_dbclk {
+ gpio2_dbclk: gpio2_dbclk at 1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1566,7 +1582,7 @@
reg = <0x1760>;
};
- gpio3_dbclk: gpio3_dbclk {
+ gpio3_dbclk: gpio3_dbclk at 1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1574,7 +1590,7 @@
reg = <0x1768>;
};
- gpio4_dbclk: gpio4_dbclk {
+ gpio4_dbclk: gpio4_dbclk at 1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1582,7 +1598,7 @@
reg = <0x1770>;
};
- gpio5_dbclk: gpio5_dbclk {
+ gpio5_dbclk: gpio5_dbclk at 1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1590,7 +1606,7 @@
reg = <0x1778>;
};
- gpio6_dbclk: gpio6_dbclk {
+ gpio6_dbclk: gpio6_dbclk at 1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1598,7 +1614,7 @@
reg = <0x1780>;
};
- gpio7_dbclk: gpio7_dbclk {
+ gpio7_dbclk: gpio7_dbclk at 1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1606,7 +1622,7 @@
reg = <0x1810>;
};
- gpio8_dbclk: gpio8_dbclk {
+ gpio8_dbclk: gpio8_dbclk at 1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1614,7 +1630,7 @@
reg = <0x1818>;
};
- mmc1_clk32k: mmc1_clk32k {
+ mmc1_clk32k: mmc1_clk32k at 1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1622,7 +1638,7 @@
reg = <0x1328>;
};
- mmc2_clk32k: mmc2_clk32k {
+ mmc2_clk32k: mmc2_clk32k at 1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1630,7 +1646,7 @@
reg = <0x1330>;
};
- mmc3_clk32k: mmc3_clk32k {
+ mmc3_clk32k: mmc3_clk32k at 1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1638,7 +1654,7 @@
reg = <0x1820>;
};
- mmc4_clk32k: mmc4_clk32k {
+ mmc4_clk32k: mmc4_clk32k at 1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1646,7 +1662,7 @@
reg = <0x1828>;
};
- sata_ref_clk: sata_ref_clk {
+ sata_ref_clk: sata_ref_clk at 1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
@@ -1654,7 +1670,7 @@
reg = <0x1388>;
};
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
@@ -1662,7 +1678,7 @@
reg = <0x13f0>;
};
- usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m at 1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
@@ -1670,7 +1686,7 @@
reg = <0x1340>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k at 640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1678,7 +1694,7 @@
reg = <0x0640>;
};
- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+ usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k at 688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1686,7 +1702,7 @@
reg = <0x0688>;
};
- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k at 698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
@@ -1694,7 +1710,7 @@
reg = <0x0698>;
};
- atl_dpll_clk_mux: atl_dpll_clk_mux {
+ atl_dpll_clk_mux: atl_dpll_clk_mux at c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
@@ -1702,7 +1718,7 @@
reg = <0x0c00>;
};
- atl_gfclk_mux: atl_gfclk_mux {
+ atl_gfclk_mux: atl_gfclk_mux at c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
@@ -1710,16 +1726,15 @@
reg = <0x0c00>;
};
- gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ rmii_50mhz_clk_mux: rmii_50mhz_clk_mux at 13d0 {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_gmac_m2_ck>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
- ti,dividers = <2>;
};
- gmac_rft_clk_mux: gmac_rft_clk_mux {
+ gmac_rft_clk_mux: gmac_rft_clk_mux at 13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
@@ -1727,7 +1742,7 @@
reg = <0x13d0>;
};
- gpu_core_gclk_mux: gpu_core_gclk_mux {
+ gpu_core_gclk_mux: gpu_core_gclk_mux at 1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1735,7 +1750,7 @@
reg = <0x1220>;
};
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1743,7 +1758,7 @@
reg = <0x1220>;
};
- l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div at e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&wkupaon_iclk_mux>;
@@ -1752,7 +1767,7 @@
ti,dividers = <8>, <16>, <32>;
};
- mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+ mcasp2_ahclkr_mux: mcasp2_ahclkr_mux at 1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1760,7 +1775,7 @@
reg = <0x1860>;
};
- mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+ mcasp2_ahclkx_mux: mcasp2_ahclkx_mux at 1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1768,7 +1783,7 @@
reg = <0x1860>;
};
- mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+ mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux at 1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1776,7 +1791,7 @@
reg = <0x1860>;
};
- mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+ mcasp3_ahclkx_mux: mcasp3_ahclkx_mux at 1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1784,7 +1799,7 @@
reg = <0x1868>;
};
- mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+ mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux at 1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1792,7 +1807,7 @@
reg = <0x1868>;
};
- mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+ mcasp4_ahclkx_mux: mcasp4_ahclkx_mux at 1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1800,7 +1815,7 @@
reg = <0x1898>;
};
- mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+ mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux at 1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1808,7 +1823,7 @@
reg = <0x1898>;
};
- mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+ mcasp5_ahclkx_mux: mcasp5_ahclkx_mux at 1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1816,7 +1831,7 @@
reg = <0x1878>;
};
- mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+ mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux at 1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1824,7 +1839,7 @@
reg = <0x1878>;
};
- mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+ mcasp6_ahclkx_mux: mcasp6_ahclkx_mux at 1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1832,7 +1847,7 @@
reg = <0x1904>;
};
- mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+ mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux at 1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1840,7 +1855,7 @@
reg = <0x1904>;
};
- mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+ mcasp7_ahclkx_mux: mcasp7_ahclkx_mux at 1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1848,7 +1863,7 @@
reg = <0x1908>;
};
- mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux at 1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1856,7 +1871,7 @@
reg = <0x1908>;
};
- mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+ mcasp8_ahclkx_mux: mcasp8_ahclkx_mux at 1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1864,7 +1879,7 @@
reg = <0x1890>;
};
- mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+ mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux at 1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1872,7 +1887,7 @@
reg = <0x1890>;
};
- mmc1_fclk_mux: mmc1_fclk_mux {
+ mmc1_fclk_mux: mmc1_fclk_mux at 1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1880,7 +1895,7 @@
reg = <0x1328>;
};
- mmc1_fclk_div: mmc1_fclk_div {
+ mmc1_fclk_div: mmc1_fclk_div at 1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
@@ -1890,7 +1905,7 @@
ti,index-power-of-two;
};
- mmc2_fclk_mux: mmc2_fclk_mux {
+ mmc2_fclk_mux: mmc2_fclk_mux at 1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1898,7 +1913,7 @@
reg = <0x1330>;
};
- mmc2_fclk_div: mmc2_fclk_div {
+ mmc2_fclk_div: mmc2_fclk_div at 1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
@@ -1908,7 +1923,7 @@
ti,index-power-of-two;
};
- mmc3_gfclk_mux: mmc3_gfclk_mux {
+ mmc3_gfclk_mux: mmc3_gfclk_mux at 1820 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1916,7 +1931,7 @@
reg = <0x1820>;
};
- mmc3_gfclk_div: mmc3_gfclk_div {
+ mmc3_gfclk_div: mmc3_gfclk_div at 1820 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
@@ -1926,7 +1941,7 @@
ti,index-power-of-two;
};
- mmc4_gfclk_mux: mmc4_gfclk_mux {
+ mmc4_gfclk_mux: mmc4_gfclk_mux at 1828 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1934,7 +1949,7 @@
reg = <0x1828>;
};
- mmc4_gfclk_div: mmc4_gfclk_div {
+ mmc4_gfclk_div: mmc4_gfclk_div at 1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
@@ -1944,7 +1959,7 @@
ti,index-power-of-two;
};
- qspi_gfclk_mux: qspi_gfclk_mux {
+ qspi_gfclk_mux: qspi_gfclk_mux at 1838 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
@@ -1952,7 +1967,7 @@
reg = <0x1838>;
};
- qspi_gfclk_div: qspi_gfclk_div {
+ qspi_gfclk_div: qspi_gfclk_div at 1838 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
@@ -1962,7 +1977,7 @@
ti,index-power-of-two;
};
- timer10_gfclk_mux: timer10_gfclk_mux {
+ timer10_gfclk_mux: timer10_gfclk_mux at 1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1970,7 +1985,7 @@
reg = <0x1728>;
};
- timer11_gfclk_mux: timer11_gfclk_mux {
+ timer11_gfclk_mux: timer11_gfclk_mux at 1730 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1978,7 +1993,7 @@
reg = <0x1730>;
};
- timer13_gfclk_mux: timer13_gfclk_mux {
+ timer13_gfclk_mux: timer13_gfclk_mux at 17c8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1986,7 +2001,7 @@
reg = <0x17c8>;
};
- timer14_gfclk_mux: timer14_gfclk_mux {
+ timer14_gfclk_mux: timer14_gfclk_mux at 17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1994,7 +2009,7 @@
reg = <0x17d0>;
};
- timer15_gfclk_mux: timer15_gfclk_mux {
+ timer15_gfclk_mux: timer15_gfclk_mux at 17d8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2002,7 +2017,7 @@
reg = <0x17d8>;
};
- timer16_gfclk_mux: timer16_gfclk_mux {
+ timer16_gfclk_mux: timer16_gfclk_mux at 1830 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2010,7 +2025,7 @@
reg = <0x1830>;
};
- timer2_gfclk_mux: timer2_gfclk_mux {
+ timer2_gfclk_mux: timer2_gfclk_mux at 1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2018,7 +2033,7 @@
reg = <0x1738>;
};
- timer3_gfclk_mux: timer3_gfclk_mux {
+ timer3_gfclk_mux: timer3_gfclk_mux at 1740 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2026,7 +2041,7 @@
reg = <0x1740>;
};
- timer4_gfclk_mux: timer4_gfclk_mux {
+ timer4_gfclk_mux: timer4_gfclk_mux at 1748 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2034,7 +2049,7 @@
reg = <0x1748>;
};
- timer9_gfclk_mux: timer9_gfclk_mux {
+ timer9_gfclk_mux: timer9_gfclk_mux at 1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2042,7 +2057,7 @@
reg = <0x1750>;
};
- uart1_gfclk_mux: uart1_gfclk_mux {
+ uart1_gfclk_mux: uart1_gfclk_mux at 1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2050,7 +2065,7 @@
reg = <0x1840>;
};
- uart2_gfclk_mux: uart2_gfclk_mux {
+ uart2_gfclk_mux: uart2_gfclk_mux at 1848 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2058,7 +2073,7 @@
reg = <0x1848>;
};
- uart3_gfclk_mux: uart3_gfclk_mux {
+ uart3_gfclk_mux: uart3_gfclk_mux at 1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2066,7 +2081,7 @@
reg = <0x1850>;
};
- uart4_gfclk_mux: uart4_gfclk_mux {
+ uart4_gfclk_mux: uart4_gfclk_mux at 1858 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2074,7 +2089,7 @@
reg = <0x1858>;
};
- uart5_gfclk_mux: uart5_gfclk_mux {
+ uart5_gfclk_mux: uart5_gfclk_mux at 1870 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2082,7 +2097,7 @@
reg = <0x1870>;
};
- uart7_gfclk_mux: uart7_gfclk_mux {
+ uart7_gfclk_mux: uart7_gfclk_mux at 18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2090,7 +2105,7 @@
reg = <0x18d0>;
};
- uart8_gfclk_mux: uart8_gfclk_mux {
+ uart8_gfclk_mux: uart8_gfclk_mux at 18e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2098,7 +2113,7 @@
reg = <0x18e0>;
};
- uart9_gfclk_mux: uart9_gfclk_mux {
+ uart9_gfclk_mux: uart9_gfclk_mux at 18e8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2106,7 +2121,7 @@
reg = <0x18e8>;
};
- vip1_gclk_mux: vip1_gclk_mux {
+ vip1_gclk_mux: vip1_gclk_mux at 1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2114,7 +2129,7 @@
reg = <0x1020>;
};
- vip2_gclk_mux: vip2_gclk_mux {
+ vip2_gclk_mux: vip2_gclk_mux at 1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2122,7 +2137,7 @@
reg = <0x1028>;
};
- vip3_gclk_mux: vip3_gclk_mux {
+ vip3_gclk_mux: vip3_gclk_mux at 1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2139,11 +2154,43 @@
};
&scm_conf_clocks {
- dss_deshdcp_clk: dss_deshdcp_clk {
+ dss_deshdcp_clk: dss_deshdcp_clk at 558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk at 558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <20>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk at 558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <21>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk at 558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <22>;
+ reg = <0x0558>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x6c4>;
+ };
};
diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clk/ti-dra7-atl.h
new file mode 100644
index 0000000..42dd416
--- /dev/null
+++ b/include/dt-bindings/clk/ti-dra7-atl.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for DRA7 ATL (Audio Tracking Logic)
+ *
+ * The constants defined in this header are used in dts files
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
+#define _DT_BINDINGS_CLK_DRA7_ATL_H
+
+#define DRA7_ATL_WS_MCASP1_FSR 0
+#define DRA7_ATL_WS_MCASP1_FSX 1
+#define DRA7_ATL_WS_MCASP2_FSR 2
+#define DRA7_ATL_WS_MCASP2_FSX 3
+#define DRA7_ATL_WS_MCASP3_FSX 4
+#define DRA7_ATL_WS_MCASP4_FSX 5
+#define DRA7_ATL_WS_MCASP5_FSX 6
+#define DRA7_ATL_WS_MCASP6_FSX 7
+#define DRA7_ATL_WS_MCASP7_FSX 8
+#define DRA7_ATL_WS_MCASP8_FSX 9
+#define DRA7_ATL_WS_MCASP8_AHCLKX 10
+#define DRA7_ATL_WS_XREF_CLK3 11
+#define DRA7_ATL_WS_XREF_CLK0 12
+#define DRA7_ATL_WS_XREF_CLK1 13
+#define DRA7_ATL_WS_XREF_CLK2 14
+#define DRA7_ATL_WS_OSC1_X1 15
+
+#endif
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index 7448edf..5c75e80 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -30,6 +30,26 @@
#define MUX_MODE14 0xe
#define MUX_MODE15 0xf
+/* Certain pins need virtual mode, but note: they may glitch */
+#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
+#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
+#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
+#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
+#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
+#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
+#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
+#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
+#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
+#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
+#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
+#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
+#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
+#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
+#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
+#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
+
+#define MODE_SELECT (1 << 8)
+
#define PULL_ENA (0 << 16)
#define PULL_DIS (1 << 16)
#define PULL_UP (1 << 17)
@@ -47,5 +67,11 @@
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
+
#endif
--
2.10.1
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