[U-Boot] [PATCH v3 2/9] ARM: DTS: stm32: add stm32f746-disco device tree files
Michael Kurz
michi.kurz at gmail.com
Thu Nov 24 20:10:40 CET 2016
This patch adds the DTS source files needed for stm32f746-disco board
The files are based on the stm32f429/469 files from current linux
kernel.
Signed-off-by: Michael Kurz <michi.kurz at gmail.com>
Acked-by: Vikas MANOCHA <vikas.manocha at st.com>
---
Changes in v3:
- Split pin control files of from device tree patch
- Add Acked-by tag to 'add stm32f746-disco device tree files'
Changes in v2: None
arch/arm/dts/Makefile | 2 +
arch/arm/dts/armv7-m.dtsi | 24 +++
arch/arm/dts/stm32f746-disco.dts | 154 +++++++++++++++
arch/arm/dts/stm32f746.dtsi | 397 ++++++++++++++++++++++++++++++++++++++
configs/stm32f746-disco_defconfig | 1 +
5 files changed, 578 insertions(+)
create mode 100644 arch/arm/dts/armv7-m.dtsi
create mode 100644 arch/arm/dts/stm32f746-disco.dts
create mode 100644 arch/arm/dts/stm32f746.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2c5b2f2..b340f82 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -157,6 +157,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
+dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb
+
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/dts/armv7-m.dtsi b/arch/arm/dts/armv7-m.dtsi
new file mode 100644
index 0000000..e0a6bf2
--- /dev/null
+++ b/arch/arm/dts/armv7-m.dtsi
@@ -0,0 +1,24 @@
+#include "skeleton.dtsi"
+
+/ {
+ nvic: interrupt-controller at e000e100 {
+ compatible = "arm,armv7m-nvic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe000e100 0xc00>;
+ };
+
+ systick: timer at e000e010 {
+ compatible = "arm,armv7m-systick";
+ reg = <0xe000e010 0x10>;
+ status = "disabled";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&nvic>;
+ ranges;
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
new file mode 100644
index 0000000..7b652f0
--- /dev/null
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2016 - Michael Kurz <michi.kurz at gmail.com>
+ *
+ * Based on:
+ * stm32f469-disco.dts from Linux
+ * Copyright 2016 - Lee Jones <lee.jones at linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32F746-DISCO board";
+ compatible = "st,stm32f746-disco", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/ram rdinit=/linuxrc";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x800000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ spi0 = &qspi;
+ };
+
+ soc {
+ pin-controller {
+ usart1_pins_disco: usart1 at 0 {
+ pins1 {
+ pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
+
+ ethernet_pins_disco: ethernet at 0 {
+ pins {
+ pinmux = <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>;
+ slew-rate = <2>;
+ };
+ };
+
+ qspi_pins_disco: qspi at 0 {
+ pins {
+ pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+ <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+ <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
+ <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
+ <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+ <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+ slew-rate = <2>;
+ };
+ };
+ };
+ };
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&mac {
+ status = "okay";
+ pinctrl-0 = <ðernet_pins_disco>;
+ pinctrl-names = "default";
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ };
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_disco>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins_disco>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ qflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a13", "spi-flash";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ memory-map = <0x90000000 0x1000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
new file mode 100644
index 0000000..3a6d1b8
--- /dev/null
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -0,0 +1,397 @@
+/*
+ * Copyright 2016 - Michael Kurz <michi.kurz at gmail.com>
+ *
+ * Based on:
+ * stm32f429.dtsi from Linux
+ * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32 at gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+
+/ {
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+ };
+
+ soc {
+ dma-ranges = <0xc0000000 0x0 0x10000000>;
+
+ timer2: timer at 40000000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000000 0x400>;
+ interrupts = <28>;
+ clocks = <&rcc 0 128>;
+ status = "disabled";
+ };
+
+ timer3: timer at 40000400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000400 0x400>;
+ interrupts = <29>;
+ clocks = <&rcc 0 129>;
+ status = "disabled";
+ };
+
+ timer4: timer at 40000800 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000800 0x400>;
+ interrupts = <30>;
+ clocks = <&rcc 0 130>;
+ status = "disabled";
+ };
+
+ timer5: timer at 40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc 0 131>;
+ };
+
+ timer6: timer at 40001000 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001000 0x400>;
+ interrupts = <54>;
+ clocks = <&rcc 0 132>;
+ status = "disabled";
+ };
+
+ timer7: timer at 40001400 {
+ compatible = "st,stm32-timer";
+ reg = <0x40001400 0x400>;
+ interrupts = <55>;
+ clocks = <&rcc 0 133>;
+ status = "disabled";
+ };
+
+ usart2: serial at 40004400 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ clocks = <&rcc 0 145>;
+ status = "disabled";
+ };
+
+ usart3: serial at 40004800 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40004800 0x400>;
+ interrupts = <39>;
+ clocks = <&rcc 0 146>;
+ status = "disabled";
+ };
+
+ usart4: serial at 40004c00 {
+ compatible = "st,stm32-uart";
+ reg = <0x40004c00 0x400>;
+ interrupts = <52>;
+ clocks = <&rcc 0 147>;
+ status = "disabled";
+ };
+
+ usart5: serial at 40005000 {
+ compatible = "st,stm32-uart";
+ reg = <0x40005000 0x400>;
+ interrupts = <53>;
+ clocks = <&rcc 0 148>;
+ status = "disabled";
+ };
+
+ usart7: serial at 40007800 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40007800 0x400>;
+ interrupts = <82>;
+ clocks = <&rcc 0 158>;
+ status = "disabled";
+ };
+
+ usart8: serial at 40007c00 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40007c00 0x400>;
+ interrupts = <83>;
+ clocks = <&rcc 0 159>;
+ status = "disabled";
+ };
+
+ usart1: serial at 40011000 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <37>;
+ clocks = <&rcc 0 164>;
+ status = "disabled";
+ };
+
+ usart6: serial at 40011400 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40011400 0x400>;
+ interrupts = <71>;
+ clocks = <&rcc 0 165>;
+ status = "disabled";
+ };
+
+ spi1: spi at 40013000 {
+ compatible = "st,stm32-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40013000 0x400>;
+ interrupts = <35>;
+ clock-names = "spi1";
+ clocks = <&rcc 0 172>;
+ num-cs = <1>;
+ big-endian;
+ status = "disabled";
+ };
+
+ syscfg: system-config at 40013800 {
+ compatible = "syscon";
+ reg = <0x40013800 0x400>;
+ };
+
+ exti: interrupt-controller at 40013c00 {
+ compatible = "st,stm32-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40013C00 0x400>;
+ interrupts = <1>,
+ <2>,
+ <3>,
+ <6>,
+ <7>,
+ <8>,
+ <9>,
+ <10>,
+ <23>,
+ <40>,
+ <41>,
+ <42>,
+ <62>,
+ <76>;
+ };
+
+ pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f746-pinctrl";
+ ranges = <0 0x40020000 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio at 40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 0>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio at 40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 1>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio at 40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 2>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio at 40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 3>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio at 40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 4>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio at 40021400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1400 0x400>;
+ clocks = <&rcc 0 5>;
+ st,bank-name = "GPIOF";
+ };
+
+ gpiog: gpio at 40021800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1800 0x400>;
+ clocks = <&rcc 0 6>;
+ st,bank-name = "GPIOG";
+ };
+
+ gpioh: gpio at 40021c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc 0 7>;
+ st,bank-name = "GPIOH";
+ };
+
+ gpioi: gpio at 40022000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc 0 8>;
+ st,bank-name = "GPIOI";
+ };
+
+ gpioj: gpio at 40022400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2400 0x400>;
+ clocks = <&rcc 0 9>;
+ st,bank-name = "GPIOJ";
+ };
+
+ gpiok: gpio at 40022800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2800 0x400>;
+ clocks = <&rcc 0 10>;
+ st,bank-name = "GPIOK";
+ };
+ };
+
+ rcc: rcc at 40023810 {
+ #reset-cells = <1>;
+ #clock-cells = <2>;
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>;
+ };
+
+ dma1: dma-controller at 40026000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&rcc 0 21>;
+ #dma-cells = <4>;
+ };
+
+ dma2: dma-controller at 40026400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&rcc 0 22>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ };
+
+ mac: ethernet at 40028000 {
+ compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+ reg = <0x40028000 0x8000>;
+ reg-names = "stmmaceth";
+ interrupts = <61>, <62>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+ clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
+ st,syscon = <&syscfg 0x4>;
+ snps,pbl = <8>;
+ snps,mixed-burst;
+ dma-ranges;
+ status = "disabled";
+ };
+
+ usbotg_hs: usb at 40040000 {
+ compatible = "snps,dwc2";
+ dma-ranges;
+ reg = <0x40040000 0x40000>;
+ interrupts = <77>;
+ clocks = <&rcc 0 29>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ rng: rng at 50060800 {
+ compatible = "st,stm32-rng";
+ reg = <0x50060800 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 38>;
+ };
+
+ qspi: quadspi at A0001000 {
+ compatible = "st,stm32-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <92>;
+ clock-names = "qspi";
+ clocks = <&rcc 0 65>;
+ spi-max-frequency = <108000000>;
+ status = "disabled";
+ };
+ };
+};
+
+&systick {
+ clocks = <&rcc 1 0>;
+ status = "okay";
+};
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 6d71d0a..7f6a442 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_STM32=y
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
--
2.1.4
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