[U-Boot] [PATCH v2 2/8] spi: cadence_qspi: Fix baud rate calculation

[Phil Edworthy]

Hi Jagan,

On 25 November 2016 15:42 Jagan Teki wrote:
> On Fri, Nov 25, 2016 at 8:08 PM, Phil Edworthy
> <phil.edworthy at renesas.com> wrote:
> > With the existing code, when the requested SPI clock rate is near
> > to the lowest that can be achieved by the hardware (max divider
> > of the ref clock is 32), the generated clock rate is wrong.
> > For example, with a 50MHz ref clock, when asked for anything less
> > than a 1.5MHz SPI clock, the code sets up the divider to generate
> > 25MHz.
> >
> > This change fixes the calculation.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
> > ---
> > v2:
> >  - Use the DIV_ROUND_UP macro
> > ---
> >  drivers/spi/cadence_qspi_apb.c | 23 +++++++----------------
> >  1 file changed, 7 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> > index 2403e71..b9e0df7 100644
> > --- a/drivers/spi/cadence_qspi_apb.c
> > +++ b/drivers/spi/cadence_qspi_apb.c
> > @@ -273,22 +273,13 @@ void cadence_qspi_apb_config_baudrate_div(void
> *reg_base,
> >         reg = readl(reg_base + CQSPI_REG_CONFIG);
> >         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK <<
> CQSPI_REG_CONFIG_BAUD_LSB);
> >
> > -       div = ref_clk_hz / sclk_hz;
> > -
> > -       if (div > 32)
> > -               div = 32;
> > -
> > -       /* Check if even number. */
> > -       if ((div & 1)) {
> > -               div = (div / 2);
> > -       } else {
> > -               if (ref_clk_hz % sclk_hz)
> > -                       /* ensure generated SCLK doesn't exceed user
> > -                       specified sclk_hz */
> > -                       div = (div / 2);
> > -               else
> > -                       div = (div / 2) - 1;
> > -       }
> > +       /*
> > +        * The baud_div field in the config reg is 4 bits, and the ref clock is
> > +        * divided by 2 * (baud_div + 1). Round up the divider to ensure the
> > +        * SPI clock rate is less than or equal to the requested clock rate.
> > +        */
> > +       div = DIV_ROUND_UP(ref_clk_hz, sclk_hz);
> > +       div = DIV_ROUND_UP(div, 2) - 1;
> 
> What about div = (ref / (sclk * 2)) -1 that means
> div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) -1;
Yes, that is also the same result. I'll change the code.

> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com
> U-Boot, Linux | Upstream Maintainer
> Hyderabad, India.

Thanks
Phil