[U-Boot] [PATCH v2] armv8: QSPI: Add AHB bus 16MB+ size support

Yuan Yao yao.yuan at freescale.com
Wed Nov 30 04:20:25 CET 2016


From: Yuan Yao <yao.yuan at nxp.com>

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.yuan at nxp.com>
---
Changed in v2:
	Remove the CONFIG_QSPI_AHB_INIT into Kconfig.
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 38 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 configs/ls1012afrdm_qspi_defconfig                 |  1 +
 configs/ls1012aqds_qspi_defconfig                  |  1 +
 configs/ls1012ardb_qspi_defconfig                  |  1 +
 configs/ls1046ardb_qspi_defconfig                  |  1 +
 scripts/config_whitelist.txt                       |  1 +
 9 files changed, 52 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..f078712 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -71,6 +71,13 @@ config NUM_DDR_CONTROLLERS
 	default 3 if ARCH_LS2080A
 	default 1
 
+config QSPI_AHB_INIT
+	bool "Init the QSPI AHB bus"
+	help
+	  The default setting for QSPI AHB bus just support 3bytes addressing.
+	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
+	  bus for those flashes to support the full QSPI flash size.
+
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
 	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6c42387..44927b1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -373,6 +373,41 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_QSPI_AHB_INIT
+/* Enable 4bytes address support and fast read */
+int qspi_ahb_init(void)
+{
+	u32 *qspi_lut, lut_key, *qspi_key;
+
+	qspi_key = (void *)CONFIG_SYS_QSPI_ADDR + 0x300;
+	qspi_lut = (void *)CONFIG_SYS_QSPI_ADDR + 0x310;
+
+	lut_key = in_be32(qspi_key);
+
+	if (lut_key == 0x5af05af0) {
+		/* That means the register is BE */
+		out_be32(qspi_key, 0x5af05af0);
+		out_be32(qspi_key + 1, 0x00000002);
+		out_be32(qspi_lut, 0x0820040c);
+		out_be32(qspi_lut + 1, 0x1c080c08);
+		out_be32(qspi_lut + 2, 0x00002400);
+		out_be32(qspi_key, 0x5af05af0);
+		out_be32(qspi_key + 1, 0x00000001);
+	} else {
+		/* That means the register is LE */
+		out_le32(qspi_key, 0x5af05af0);
+		out_le32(qspi_key + 1, 0x00000002);
+		out_le32(qspi_lut, 0x0820040c);
+		out_le32(qspi_lut + 1, 0x1c080c08);
+		out_le32(qspi_lut + 2, 0x00002400);
+		out_le32(qspi_key, 0x5af05af0);
+		out_le32(qspi_key + 1, 0x00000001);
+	}
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -382,6 +417,9 @@ int board_late_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
 	fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_QSPI_AHB_INIT
+	qspi_ahb_init();
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..a28b1fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 2df56f7..e0cf0e4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1f3d487..c83b2eb 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -34,3 +34,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index c0514ae..27bccd1 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -38,3 +38,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 13c9f21..459682d 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -38,3 +38,4 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_QSPI_AHB_INIT=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 8508c09..fa17373 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_QSPI_AHB_INIT=y
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index d0b5e7f..8dd3e4b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -7340,6 +7340,7 @@ CONFIG_SYS_QRIO_BASE
 CONFIG_SYS_QRIO_BASE_PHYS
 CONFIG_SYS_QRIO_BR_PRELIM
 CONFIG_SYS_QRIO_OR_PRELIM
+CONFIG_SYS_QSPI_ADDR
 CONFIG_SYS_R7780MP_OLD_FLASH
 CONFIG_SYS_RAMBOOT
 CONFIG_SYS_RAM_BASE
-- 
2.1.0.27.g96db324



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