[U-Boot] [PATCH 1/2] armv8: add hooks for all cache-wide operations

[Stephen Warren]

From: Stephen Warren <swarren at nvidia.com>

SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided. These dummy
implementations are moved into C code, since there's no need to
implement them in assembly.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/cpu/armv8/cache.S                   |  6 ------
 arch/arm/cpu/armv8/cache_v8.c                | 23 ++++++++++++++++++++---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S |  4 ++--
 arch/arm/include/asm/system.h                |  5 ++++-
 arch/arm/mach-tegra/tegra186/cache.c         |  2 +-
 5 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 46f25e63f01d..23fa914dc556 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -150,12 +150,6 @@ ENTRY(__asm_invalidate_icache_all)
 	ret
 ENDPROC(__asm_invalidate_icache_all)
 
-ENTRY(__asm_flush_l3_cache)
-	mov	x0, #0			/* return status as success */
-	ret
-ENDPROC(__asm_flush_l3_cache)
-	.weak	__asm_flush_l3_cache
-
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)
  *
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cd3f6c10ae12..d2965e9878a0 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -415,25 +415,36 @@ __weak void mmu_setup(void)
 	set_sctlr(get_sctlr() | CR_M);
 }
 
+__weak int invalidate_dcache_all_l3(void)
+{
+	return 0;
+}
+
 /*
  * Performs a invalidation of the entire data cache at all levels
  */
 void invalidate_dcache_all(void)
 {
 	__asm_invalidate_dcache_all();
+	invalidate_dcache_all_l3();
+}
+
+__weak int flush_dcache_all_l3(void)
+{
+	return 0;
 }
 
 /*
  * Performs a clean & invalidation of the entire data cache at all levels.
  * This function needs to be inline to avoid using stack.
- * __asm_flush_l3_cache return status of timeout
+ * flush_dcache_all_l3 return status of timeout
  */
 inline void flush_dcache_all(void)
 {
 	int ret;
 
 	__asm_flush_dcache_all();
-	ret = __asm_flush_l3_cache();
+	ret = flush_dcache_all_l3();
 	if (ret)
 		debug("flushing dcache returns 0x%x\n", ret);
 	else
@@ -623,7 +634,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 void icache_enable(void)
 {
-	__asm_invalidate_icache_all();
+	invalidate_icache_all();
 	set_sctlr(get_sctlr() | CR_I);
 }
 
@@ -637,9 +648,15 @@ int icache_status(void)
 	return (get_sctlr() & CR_I) != 0;
 }
 
+__weak int invalidate_icache_all_l3(void)
+{
+	return 0;
+}
+
 void invalidate_icache_all(void)
 {
 	__asm_invalidate_icache_all();
+	invalidate_icache_all_l3();
 }
 
 #else	/* CONFIG_SYS_ICACHE_OFF */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a45c354..4e4ef8b7a6df 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -245,7 +245,7 @@ hnf_set_pstate:
 
 	ret
 
-ENTRY(__asm_flush_l3_cache)
+ENTRY(flush_dcache_all_l3)
 	/*
 	 * Return status in x0
 	 *    success 0
@@ -275,7 +275,7 @@ ENTRY(__asm_flush_l3_cache)
 	mov	x0, x8
 	mov	lr, x29
 	ret
-ENDPROC(__asm_flush_l3_cache)
+ENDPROC(flush_dcache_all_l3)
 #endif
 
 #ifdef CONFIG_MP
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index c18e1e3a10ee..095f3742ce60 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -93,9 +93,12 @@ void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);
 void __asm_invalidate_tlb_all(void);
 void __asm_invalidate_icache_all(void);
-int __asm_flush_l3_cache(void);
 void __asm_switch_ttbr(u64 new_ttbr);
 
+int invalidate_dcache_all_l3(void);
+int flush_dcache_all_l3(void);
+int invalidate_icache_all_l3(void);
+
 void armv8_switch_to_el2(void);
 void armv8_switch_to_el1(void);
 void gic_init(void);
diff --git a/arch/arm/mach-tegra/tegra186/cache.c b/arch/arm/mach-tegra/tegra186/cache.c
index adaed8968eb9..fb0b1142e49b 100644
--- a/arch/arm/mach-tegra/tegra186/cache.c
+++ b/arch/arm/mach-tegra/tegra186/cache.c
@@ -10,7 +10,7 @@
 #define SMC_SIP_INVOKE_MCE	0x82FFFF00
 #define MCE_SMC_ROC_FLUSH_CACHE	11
 
-int __asm_flush_l3_cache(void)
+int flush_dcache_all_l3(void)
 {
 	struct pt_regs regs = {0};
 
-- 
2.10.1