[U-Boot] [PATCH] arch: ifc: update the IFC IP input clock

Prabhakar Kushwaha prabhakar.kushwaha at nxp.com
Wed Sep 7 04:42:06 CEST 2016


> -----Original Message-----
> From: york sun
> Sent: Tuesday, September 06, 2016 9:10 PM
> To: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; u-
> boot at lists.denx.de
> Subject: Re: [PATCH] arch: ifc: update the IFC IP input clock
> 
> On 09/06/2016 04:15 AM, Prabhakar Kushwaha wrote:
> > IFC IP clock is always a constant divisor of platform clock
> > pre-defined per SoC. Clock Control register (CCR) used in
> > current implementation governs IFC IP output clock.
> >
> > So update IFC IP clock to be defined as per predefined clock
> > divisor of platform clock.
> >
> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
> > ---
> >  README                                              |  3 +++
> >  arch/arm/cpu/armv7/ls102xa/clock.c                  | 10 ++--------
> >  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 ++--------
> >  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 ++--------
> >  arch/arm/include/asm/arch-fsl-layerscape/config.h   |  3 +++
> >  arch/arm/include/asm/arch-ls102xa/config.h          |  1 +
> >  arch/powerpc/cpu/mpc85xx/speed.c                    | 10 ++--------
> >  arch/powerpc/include/asm/config_mpc85xx.h           |  9 +++++++++
> >  8 files changed, 24 insertions(+), 32 deletions(-)
> 
> Prabkahar,
> 
> Two concerns here
> 
> 1, it is not only IFC for powerpc. Older SoCs have local bus. That's why
> the variable is named freq_localbus..
> 

As per my understanding, Issue is valid for eLBC SoC also.
Just wanted to confirm from internal IP team before spinning patch to fix it. 

> 2, what's the reason for this change? Is it wrong to use ccr to
> calculate the clock? Or is it because recent Layerscape SoCs have
> platform PLL different from platform clock? If the latter, can we limit
> the fix to platform clock and not changing powerpc?
> 

CCR governs the IFC output clock. 
This clock is used for synchronous NOR, NAND flashes. It is nowhere govern IFC IP internal clock. 

It is true since conception of IFC. Unfortunately code written is wrong since P1010. 
It is confusing everyone.  

--prabhakar



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