[U-Boot] [PATCH] mx6sabreauto: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values

[Stefano Babic]

On 02/08/2017 19:08, Breno Lima wrote:
> The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
> commented in the code:
> /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
> 
> Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.
> 
> Signed-off-by: Breno Lima <breno.lima at nxp.com>
> ---
>  board/freescale/mx6sabreauto/mx6sabreauto.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
> index a5703a3..cad6004 100644
> --- a/board/freescale/mx6sabreauto/mx6sabreauto.c
> +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
> @@ -806,8 +806,8 @@ static void gpr_init(void)
>  	writel(0xF00000CF, &iomux->gpr[4]);
>  	if (is_mx6dqp()) {
>  		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
> -		writel(0x007F007F, &iomux->gpr[6]);
> -		writel(0x007F007F, &iomux->gpr[7]);
> +		writel(0x77177717, &iomux->gpr[6]);
> +		writel(0x77177717, &iomux->gpr[7]);
>  	} else {
>  		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
>  		writel(0x007F007F, &iomux->gpr[6]);
> 

I think the next factorization will be to move gpr_init() into arch, as
the same code is duplicated for each board. In the meanwhile, I apply this:

Applied to -master, thanks !

Best regards,
Stefano Babic


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