[U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA

Marek Vasut marex at denx.de
Wed Dec 20 15:06:21 UTC 2017


On 12/20/2017 12:51 PM, Jan Siegmund wrote:
[...]
>>> My preferred usecase would be configuring the registers in the table below in
>>> SPL and configuring the FPGA in Linux, with a design using the FPGA-to-HPS SDRAM
>>> interface.
>>>
>>> For example, the last bits in the portcfg register define whether the
>>> FPGA-to-HPS SDRAM interface's protocol is AXI or Avalon MM. The problem is, that
>>> this register can't be written to in U-Boot, even though it is specified as rw
>>> [3]. Can this register just be set by programming the FPGA?
>>
>> You might need to regenerate the SPL if you changed those kinds of
>> settings. The SPL programs these based on the handoff files IIRC.
> 
> I generated the headers using the bsp-editor from Quartus 17 and converted them
> using the qts-filter.sh script in U-Boot. Since then, I did not change any settings.
> 
> sdram.h in board/.../qts and mach-socfpga/
> 
> 	#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN	0
> 
> 	#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB		10
> 
> wrap_sdram_config.c
> 	.port_cfg =
> 		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
> 			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
> 
> sdram.c
> 	debug("Configuring PORTCFG\n");
> 	writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
> 
> When I add some debug printing around the code shown above, SPL console shows this:
> 
> U-Boot SPL 2018.01-rc1-00129-ga8548b9-dirty (Dec 18 2017 - 14:13:21)
> Content of ffc2507c is 3f
> Wrote 0 to ffc2507c
> Content of ffc2507c is 3f
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC1
> 
> Maybe the portprotocol part of portcfg is just a status register. But then
> again, why would it be specified as rw?

It should be RW actually.

> Do you have any idea what I might be missing, to get the f2s running without
> programming the FPGA?
CCing Dinh and Chin.

-- 
Best regards,
Marek Vasut


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