[U-Boot] [PATCH v1 2/2] sunxi (sun50i): improved USB support for sun50i (A64)

[Maxime Ripard]

Hi,

On Fri, Feb 17, 2017 at 06:41:17PM +0100, Philipp Tomsich wrote:
>  #if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
> +	/* On the A64-uQ7 (Lynx) we could do without opening OHCI for
> +	 * HCI1, as the on-module hubs will do the transaction
> +	 * translation.
> +	 *
> +	 * Until this is converted to the driver model (and can
> +	 * finally go away), it won't do any harm to have this here...
> +	 */

I'm not sure board specific comments make sense in generic code.

>  	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
>  #endif
>  	priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
>  	priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
>  	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
>  	priv->phy_index++; /* Non otg phys start at 1 */
>  
>  	setbits_le32(&ccm->ahb_gate0,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>  	setbits_le32(&ccm->ahb_reset0_cfg,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
>  #endif
>  
>  	sunxi_usb_phy_init(priv->phy_index);
> +#if defined(CONFIG_MACH_SUN50I)
> +	/* For the HCI blocks, the PHYCTL register is at 0x810, so
> +	   it's an extra 0x400 for the EHCI block.  This should go
> +	   away once the PHYs use the driver model.  */

This is not the proper comment style.

> +	sunxi_usb_phy_clear_SIDDP((void *)hccr + 0x400);
> +#endif
> +	sunxi_usb_phy_passby(priv->phy_index, true);
>  	sunxi_usb_phy_power_on(priv->phy_index);
>  
>  	hcor = (struct ehci_hcor *)((uintptr_t)hccr +
>  				    HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>  
>  	return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
>  }
>  
>  static int ehci_usb_remove(struct udevice *dev)
>  {
>  	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>  	struct ehci_sunxi_priv *priv = dev_get_priv(dev);
>  	int ret;
>  
>  	ret = ehci_deregister(dev);
>  	if (ret)
>  		return ret;
>  
> +	sunxi_usb_phy_passby(priv->phy_index, false);
>  	sunxi_usb_phy_exit(priv->phy_index);
>  
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>  	clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
>  #endif
>  	clrbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
>  
>  	return 0;
>  }
>  
> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
> index 0c45eec..047c3a9 100644
> --- a/drivers/usb/host/ohci-sunxi.c
> +++ b/drivers/usb/host/ohci-sunxi.c
> @@ -35,60 +35,68 @@ struct ohci_sunxi_priv {
>  static int ohci_usb_probe(struct udevice *dev)
>  {
>  	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>  	struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
>  	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>  	struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
>  	int extra_ahb_gate_mask = 0;
>  
>  	bus_priv->companion = true;
>  
>  	/*
>  	 * This should go away once we've moved to the driver model for
>  	 * clocks resp. phys.
>  	 */
>  	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
>  #ifdef CONFIG_MACH_SUN8I_H3
>  	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>  #endif
>  	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>  	priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
>  	priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
>  	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
>  	priv->usb_gate_mask <<= priv->phy_index;
>  	priv->phy_index++; /* Non otg phys start at 1 */
>  
>  	setbits_le32(&ccm->ahb_gate0,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
>  	setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>  	setbits_le32(&ccm->ahb_reset0_cfg,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
>  #endif
>  
>  	sunxi_usb_phy_init(priv->phy_index);
> +#if defined(CONFIG_MACH_SUN50I)
> +	/* For the HCI blocks, the PHYCTL register is at 0x810, so it's
> +	   an extra 0x400 for the EHCI block.  This should go away once
> +	   the PHYs use the driver model.  */

Ditto.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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