[U-Boot] [PATCH 10/20] arm: socfpga: add misc support for Arria 10

[Marek Vasut]

On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> Add misc support for Arria 10 and minor fix on misc Gen5.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile            |   1 +
>  arch/arm/mach-socfpga/include/mach/misc.h |   6 +
>  arch/arm/mach-socfpga/misc_arria10.c      | 262 ++++++++++++++++++++++++++++++
>  arch/arm/mach-socfpga/misc_gen5.c         |   3 +-
>  4 files changed, 271 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-socfpga/misc_arria10.c

[...]

> +/*
> + * This function looking the 1st encounter UART peripheral,
> + * and then return its offset of the dedicated/shared IO pin
> + * mux. offset value (zero and above).
> + */
> +static int find_peripheral_uart(const void *blob,
> +	int child, const char *node_name)
> +{
> +	int len;
> +	fdt_addr_t base_addr = 0;
> +	fdt_size_t size;
> +	const u32 *cell;
> +	u32 value, offset = 0;
> +
> +	base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
> +	if (base_addr != FDT_ADDR_T_NONE) {
> +		cell = fdt_getprop(blob, child, "pinctrl-single,pins",
> +			&len);
> +		if (cell != NULL) {
> +			for (; len > 0; len -= (2 * sizeof(u32))) {

len == 0 is not handled ?

> +				offset = fdt32_to_cpu(*cell++);
> +				value = fdt32_to_cpu(*cell++);
> +				/* Found UART peripheral */
> +				if (0x0D == value)
> +					return offset;
> +			}
> +		}
> +	}
> +	return -1;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART peripheral,

s/looking/looks up/ ?

> + * and then return its offset of the dedicated/shared IO pin
> + * mux. UART peripheral is found if the offset is not in negative
> + * value.
> + */
> +static int is_peripheral_uart_true(const void *blob,
> +	int node, const char *child_name)
> +{
> +	int child, len;
> +	const char *node_name;
> +
> +	child = fdt_first_subnode(blob, node);
> +
> +	if (child < 0)
> +		return -1;

errno.h

> +	node_name = fdt_get_name(blob, child, &len);
> +
> +	while (node_name) {
> +		if (!strcmp(child_name, node_name))
> +			return find_peripheral_uart(blob, child, node_name);
> +
> +		child = fdt_next_subnode(blob, child);
> +
> +		if (child < 0)
> +			break;
> +
> +		node_name = fdt_get_name(blob, child, &len);
> +	}
> +
> +	return -1;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART dedicated IO peripheral,
> + * and then return based address of the 1st encounter UART dedicated
> + * IO peripheral.
> + */
> +unsigned int dedicated_uart_com_port(const void *blob)
> +{
> +	int node;
> +
> +	node = fdtdec_next_compatible(blob, 0,
> +		 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> +	if (node < 0)
> +		return 0;
> +
> +	if (0 <= is_peripheral_uart_true(blob, node, "dedicated"))
> +		return SOCFPGA_UART1_ADDRESS;
> +	else
> +		return 0;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART shared IO peripheral, and then
> + * return based address of the 1st encounter UART shared IO peripheral.
> + */
> +unsigned int shared_uart_com_port(const void *blob)
> +{
> +	int node, ret;
> +
> +	node = fdtdec_next_compatible(blob, 0,
> +		 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
> +
> +	if (node < 0)
> +		return 0;
> +
> +	ret = is_peripheral_uart_true(blob, node, "shared");
> +
> +	if (PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 == ret ||
> +	    PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 == ret ||
> +	    PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 == ret)
> +		return SOCFPGA_UART0_ADDRESS;
> +	else if (PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 == ret ||
> +		PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 == ret ||
> +		PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 == ret)
> +		return SOCFPGA_UART1_ADDRESS;
> +	else
> +		return 0;
> +}
> +
> +/*
> + * This function looking the 1st encounter UART peripheral, and then return
> + * base address of the 1st encounter UART peripheral.
> + */
> +unsigned int uart_com_port(const void *blob)

This is referenced earlier in the patchset , it should be added earlier
if possible.

> +{
> +	unsigned int ret;
> +
> +	ret = dedicated_uart_com_port(blob);
> +
> +	if (ret)
> +		return ret;
> +
> +	return shared_uart_com_port(blob);
> +}
> +
> +/*
> + * Print CPU information
> + */
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> +	const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>
> +			  SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
> +
> +	puts("CPU:   Altera SoCFPGA Arria 10\n");
> +
> +	printf("BOOT:  %s\n", bsel_str[bsel].name);
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_ARCH_MISC_INIT
> +int arch_misc_init(void)
> +{
> +	return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index f870e1f..3b8ce11 100755
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -200,7 +200,8 @@ static int socfpga_fpga_id(const bool print_id)
>  #if defined(CONFIG_DISPLAY_CPUINFO)
>  int print_cpuinfo(void)
>  {
> -	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> +	const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>
> +			  SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
>  
>  	puts("CPU:   Altera SoCFPGA Platform\n");
>  	socfpga_fpga_id(1);
> 


-- 
Best regards,
Marek Vasut