[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb nodes in dts

[yuantian.tang at nxp.com]

From: Tang Yuantian <Yuantian.Tang at nxp.com>

The LS1046A processor has three integrated USB 3.0 controllers
(USB1, USB2, and USB3) that allow direct connection to the USB
ports with appropriate protection circuitry and power supplies.
USB1 and USB2 ports are powered by a NX5P2190UK device, which
supplies 5v power at up to 1.2 A. The power enable and
power-fault-detect pins are connected to the LS1046A processor
via CPLD for individual port management.

Signed-off-by: Tang Yuantian <yuantian.tang at nxp.com>
---
 arch/arm/dts/fsl-ls1046a.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index aaf0ae9..408e81e 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -217,6 +217,27 @@
 			status = "disabled";
 		};
 
+		usb0: usb at 2f00000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x2f00000 0x0 0x10000>;
+			interrupts = <0 60 4>;
+			dr_mode = "host";
+		};
+
+		usb1: usb at 3000000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x3000000 0x0 0x10000>;
+			interrupts = <0 61 4>;
+			dr_mode = "host";
+		};
+
+		usb2: usb at 3100000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 63 4>;
+			dr_mode = "host";
+		};
+
 		pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
-- 
2.1.0.27.g96db324