[U-Boot] [U-Boot,3/8] rockchip: rk3128: add clock driver
Philipp Tomsich
philipp.tomsich at theobroma-systems.com
Thu Nov 23 13:56:00 UTC 2017
On Wed, 27 Sep 2017, Kever Yang wrote:
> Add rk3128 clock driver and cru structure definition.
>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
See below for requested changes.
> ---
>
> arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 173 ++++++++++++
> arch/arm/mach-rockchip/rk3128/Makefile | 1 +
> arch/arm/mach-rockchip/rk3128/clk_rk3128.c | 32 +++
> drivers/clk/rockchip/Makefile | 3 +-
> drivers/clk/rockchip/clk_rk3128.c | 350 ++++++++++++++++++++++++
> 5 files changed, 558 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3128.h
> create mode 100644 arch/arm/mach-rockchip/rk3128/clk_rk3128.c
> create mode 100644 drivers/clk/rockchip/clk_rk3128.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
> new file mode 100644
> index 0000000..f511bd0
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
> @@ -0,0 +1,173 @@
> +/*
> + * Copyright (c) 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_CRU_RK3128_H
> +#define _ASM_ARCH_CRU_RK3128_H
> +
> +#include <common.h>
> +
> +#define MHz 1000000
> +#define OSC_HZ (24 * MHz)
> +
> +#define APLL_HZ (600 * MHz)
> +#define GPLL_HZ (594 * MHz)
> +
> +#define CORE_PERI_HZ 150000000
> +#define CORE_ACLK_HZ 300000000
> +
> +#define BUS_ACLK_HZ 148500000
> +#define BUS_HCLK_HZ 148500000
> +#define BUS_PCLK_HZ 74250000
> +
> +#define PERI_ACLK_HZ 148500000
> +#define PERI_HCLK_HZ 148500000
> +#define PERI_PCLK_HZ 74250000
> +
> +/* Private data for the clock driver - used by rockchip_get_cru() */
> +struct rk3128_clk_priv {
> + struct rk3128_cru *cru;
> + ulong rate;
The rate field seems unused throughout this patch.
What is it used for?
> +};
> +
> +struct rk3128_cru {
> + struct rk3128_pll {
> + unsigned int con0;
> + unsigned int con1;
> + unsigned int con2;
> + unsigned int con3;
> + } pll[4];
> + unsigned int cru_mode_con;
> + unsigned int cru_clksel_con[35];
> + unsigned int cru_clkgate_con[11];
> + unsigned int reserved;
> + unsigned int cru_glb_srst_fst_value;
> + unsigned int cru_glb_srst_snd_value;
> + unsigned int reserved1[2];
> + unsigned int cru_softrst_con[9];
> + unsigned int cru_misc_con;
> + unsigned int reserved2[2];
> + unsigned int cru_glb_cnt_th;
> + unsigned int reserved3[3];
> + unsigned int cru_glb_rst_st;
> + unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
> + unsigned int cru_sdmmc_con[2];
> + unsigned int cru_sdio_con[2];
> + unsigned int reserved5[2];
> + unsigned int cru_emmc_con[2];
> + unsigned int reserved6[4];
> + unsigned int cru_pll_prg_en;
> +};
> +check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
> +
> +struct pll_div {
> + u32 refdiv;
> + u32 fbdiv;
> + u32 postdiv1;
> + u32 postdiv2;
> + u32 frac;
> +};
> +
> +enum {
> + /* PLLCON0*/
> + PLL_POSTDIV1_SHIFT = 12,
> + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
> + PLL_FBDIV_SHIFT = 0,
> + PLL_FBDIV_MASK = 0xfff,
> +
> + /* PLLCON1 */
> + PLL_RST_SHIFT = 14,
> + PLL_PD_SHIFT = 13,
> + PLL_PD_MASK = 1 << PLL_PD_SHIFT,
> + PLL_DSMPD_SHIFT = 12,
> + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
> + PLL_LOCK_STATUS_SHIFT = 10,
> + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
> + PLL_POSTDIV2_SHIFT = 6,
> + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
> + PLL_REFDIV_SHIFT = 0,
> + PLL_REFDIV_MASK = 0x3f,
> +
> + /* CRU_MODE */
> + GPLL_MODE_SHIFT = 12,
> + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
> + GPLL_MODE_SLOW = 0,
> + GPLL_MODE_NORM,
> + GPLL_MODE_DEEP,
> + DPLL_MODE_SHIFT = 4,
> + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
> + DPLL_MODE_SLOW = 0,
> + DPLL_MODE_NORM,
> + APLL_MODE_SHIFT = 0,
> + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
> + APLL_MODE_SLOW = 0,
> + APLL_MODE_NORM,
> +
> + /* CRU_CLK_SEL0_CON */
> + BUS_ACLK_PLL_SEL_SHIFT = 14,
> + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
> + BUS_ACLK_PLL_SEL_CPLL = 0,
> + BUS_ACLK_PLL_SEL_GPLL,
> + BUS_ACLK_PLL_SEL_GPLL_DIV2,
> + BUS_ACLK_PLL_SEL_GPLL_DIV3,
> + BUS_ACLK_DIV_SHIFT = 8,
> + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
> + CORE_CLK_PLL_SEL_SHIFT = 7,
> + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
> + CORE_CLK_PLL_SEL_APLL = 0,
> + CORE_CLK_PLL_SEL_GPLL_DIV2,
> + CORE_DIV_CON_SHIFT = 0,
> + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL1_CON */
> + BUS_PCLK_DIV_SHIFT = 12,
> + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
> + BUS_HCLK_DIV_SHIFT = 8,
> + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
> + CORE_ACLK_DIV_SHIFT = 4,
> + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
> + CORE_PERI_DIV_SHIFT = 0,
> + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
> +
> + /* CRU_CLKSEL10_CON */
> + PERI_PLL_SEL_SHIFT = 14,
> + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
> + PERI_PLL_APLL = 0,
> + PERI_PLL_DPLL,
> + PERI_PLL_GPLL,
> + PERI_PCLK_DIV_SHIFT = 12,
> + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
> + PERI_HCLK_DIV_SHIFT = 8,
> + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
> + PERI_ACLK_DIV_SHIFT = 0,
> + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
> +
> + /* CRU_CLKSEL11_CON */
> + MMC0_PLL_SHIFT = 6,
> + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
> + MMC0_SEL_APLL = 0,
> + MMC0_SEL_GPLL,
> + MMC0_SEL_GPLL_DIV2,
> + MMC0_SEL_24M,
> + MMC0_DIV_SHIFT = 0,
> + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
> +
> + /* CRU_CLKSEL12_CON */
> + EMMC_PLL_SHIFT = 14,
> + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
> + EMMC_SEL_APLL = 0,
> + EMMC_SEL_GPLL,
> + EMMC_SEL_GPLL_DIV2,
> + EMMC_SEL_24M,
> + EMMC_DIV_SHIFT = 8,
> + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
> +
> + /* CRU_SOFTRST5_CON */
> + DDRCTRL_PSRST_SHIFT = 11,
> + DDRCTRL_SRST_SHIFT = 10,
> + DDRPHY_PSRST_SHIFT = 9,
> + DDRPHY_SRST_SHIFT = 8,
> +};
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile
> index 0f63d92..50e1117 100644
> --- a/arch/arm/mach-rockchip/rk3128/Makefile
> +++ b/arch/arm/mach-rockchip/rk3128/Makefile
> @@ -6,3 +6,4 @@
>
> obj-y += rk3128.o
> obj-y += syscon_rk3128.o
> +obj-y += clk_rk3128.o
> diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c
> new file mode 100644
> index 0000000..7ca5fd3
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (c) 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3128.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(rockchip_rk3128_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3128_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index c50aff2..eae0ef6 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -1,10 +1,11 @@
> #
> -# Copyright (c) 2016 Google, Inc
> +# Copyright (c) 2017 Rockchip Electronics Co., Ltd
> #
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
> +obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
> obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
> diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
> new file mode 100644
> index 0000000..ace154f
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3128.c
> @@ -0,0 +1,350 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3128.h>
> +#include <asm/arch/hardware.h>
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rk3128-cru.h>
> +#include <linux/log2.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +enum {
> + VCO_MAX_HZ = 2400U * 1000000,
> + VCO_MIN_HZ = 600 * 1000000,
> + OUTPUT_MAX_HZ = 2400U * 1000000,
> + OUTPUT_MIN_HZ = 24 * 1000000,
> +};
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
> + .refdiv = _refdiv,\
> + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
> + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
> +
> +/* use integer mode*/
> +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
> +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
> +
> +static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
> + const struct pll_div *div)
> +{
> + int pll_id = rk_pll_id(clk_id);
> + struct rk3128_pll *pll = &cru->pll[pll_id];
> +
> + /* All PLLs have same VCO and output frequency range restrictions. */
> + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
> + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
> +
> + debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
> + pll, div->fbdiv, div->refdiv, div->postdiv1,
> + div->postdiv2, vco_hz, output_hz);
> + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
> + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
> +
> + /* use integer mode */
> + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
> + /* Power down */
> + rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
> +
> + rk_clrsetreg(&pll->con0,
> + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
> + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
> + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
> + (div->postdiv2 << PLL_POSTDIV2_SHIFT |
> + div->refdiv << PLL_REFDIV_SHIFT));
> +
> + /* Power Up */
> + rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
> +
> + /* waiting for pll lock */
> + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
> + udelay(1);
> +
> + return 0;
> +}
> +
> +static void rkclk_init(struct rk3128_cru *cru)
> +{
> + u32 aclk_div;
> + u32 hclk_div;
> + u32 pclk_div;
> +
> + /* pll enter slow-mode */
> + rk_clrsetreg(&cru->cru_mode_con,
> + GPLL_MODE_MASK | APLL_MODE_MASK,
> + GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
> + APLL_MODE_SLOW << APLL_MODE_SHIFT);
> +
> + /* init pll */
> + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
> + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
> +
> + /*
> + * select apll as cpu/core clock pll source and
> + * set up dependent divisors for PERI and ACLK clocks.
> + * core hz : apll = 1:1
> + */
> + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
> + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
> +
> + pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
> + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[0],
> + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
> + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
> + 0 << CORE_DIV_CON_SHIFT);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[1],
> + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
> + aclk_div << CORE_ACLK_DIV_SHIFT |
> + pclk_div << CORE_PERI_DIV_SHIFT);
> +
> + /*
> + * select gpll as pd_bus bus clock source and
> + * set up dependent divisors for PCLK/HCLK and ACLK clocks.
> + */
> + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
> + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
> +
> + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
> + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
> +
> + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
> + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[0],
> + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
> + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
> + aclk_div << BUS_ACLK_DIV_SHIFT);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[1],
> + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
> + pclk_div << BUS_PCLK_DIV_SHIFT |
> + hclk_div << BUS_HCLK_DIV_SHIFT);
> +
> + /*
> + * select gpll as pd_peri bus clock source and
> + * set up dependent divisors for PCLK/HCLK and ACLK clocks.
> + */
> + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
> + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
> +
> + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
> + assert((1 << hclk_div) * PERI_HCLK_HZ ==
> + PERI_ACLK_HZ && (hclk_div < 0x4));
> +
> + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
> + assert((1 << pclk_div) * PERI_PCLK_HZ ==
> + PERI_ACLK_HZ && pclk_div < 0x8);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[10],
> + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
> + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
> + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
> + pclk_div << PERI_PCLK_DIV_SHIFT |
> + hclk_div << PERI_HCLK_DIV_SHIFT |
> + aclk_div << PERI_ACLK_DIV_SHIFT);
> +
> + /* PLL enter normal-mode */
> + rk_clrsetreg(&cru->cru_mode_con,
> + GPLL_MODE_MASK | APLL_MODE_MASK,
> + GPLL_MODE_NORM << GPLL_MODE_SHIFT |
> + APLL_MODE_NORM << APLL_MODE_SHIFT);
> +}
> +
> +/* Get pll rate by id */
> +static uint32_t rkclk_pll_get_rate(struct rk3128_cru *cru,
> + enum rk_clk_id clk_id)
> +{
> + uint32_t refdiv, fbdiv, postdiv1, postdiv2;
> + uint32_t con;
> + int pll_id = rk_pll_id(clk_id);
> + struct rk3128_pll *pll = &cru->pll[pll_id];
> + static u8 clk_shift[CLK_COUNT] = {
> + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
> + GPLL_MODE_SHIFT, 0xff
> + };
> + static u32 clk_mask[CLK_COUNT] = {
> + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
> + GPLL_MODE_MASK, 0xff
> + };
> + uint shift;
> + uint mask;
> +
> + con = readl(&cru->cru_mode_con);
> + shift = clk_shift[clk_id];
> + mask = clk_mask[clk_id];
> +
> + switch ((con & mask) >> shift) {
> + case GPLL_MODE_SLOW:
> + return OSC_HZ;
> + case GPLL_MODE_NORM:
> +
Here's an empty line following the case.
> + /* normal mode */
> + con = readl(&pll->con0);
> + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
> + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
> + con = readl(&pll->con1);
> + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
> + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
> + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
> + case GPLL_MODE_DEEP:
> + default:
> + return 32768;
> + }
> +}
> +
> +static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
> + int periph)
> +{
> + uint src_rate;
> + uint div, mux;
> + u32 con;
> +
> + switch (periph) {
> + case HCLK_EMMC:
> + case SCLK_EMMC:
> + case SCLK_EMMC_SAMPLE:
> + con = readl(&cru->cru_clksel_con[12]);
> + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
> + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
> + break;
> + case HCLK_SDMMC:
> + case SCLK_SDMMC:
> + con = readl(&cru->cru_clksel_con[12]);
> + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
> + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
Can we factor this out in such a way that the value, mask, shift is set up
here, but the reading and extraction is done below in a common code-path?
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
> + return DIV_TO_RATE(src_rate, div);
> +}
> +
> +static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
> + int periph, uint freq)
> +{
> + int src_clk_div;
> + int mux;
> +
> + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
> +
> + /* mmc clock defaulg div 2 internal, need provide double in cru */
> + src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
> +
> + if (src_clk_div > 128) {
> + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
> + mux = EMMC_SEL_24M;
> + } else {
> + mux = EMMC_SEL_GPLL;
> + }
> +
> + switch (periph) {
> + case HCLK_EMMC:
> + rk_clrsetreg(&cru->cru_clksel_con[12],
> + EMMC_PLL_MASK | EMMC_DIV_MASK,
> + mux << EMMC_PLL_SHIFT |
> + (src_clk_div - 1) << EMMC_DIV_SHIFT);
> + break;
> + case HCLK_SDMMC:
> + case SCLK_SDMMC:
> + rk_clrsetreg(&cru->cru_clksel_con[11],
> + MMC0_PLL_MASK | MMC0_DIV_MASK,
> + mux << MMC0_PLL_SHIFT |
> + (src_clk_div - 1) << MMC0_DIV_SHIFT);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
> +}
> +
> +static ulong rk3128_clk_get_rate(struct clk *clk)
> +{
> + struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case 0 ... 63:
> + return rkclk_pll_get_rate(priv->cru, clk->id);
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong new_rate, gclk_rate;
> +
> + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> + switch (clk->id) {
> + case 0 ... 63:
> + return 0;
> + case HCLK_EMMC:
> + new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
> + clk->id, rate);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return new_rate;
> +}
> +
> +static struct clk_ops rk3128_clk_ops = {
> + .get_rate = rk3128_clk_get_rate,
> + .set_rate = rk3128_clk_set_rate,
> +};
> +
> +static int rk3128_clk_probe(struct udevice *dev)
> +{
> + struct rk3128_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = (struct rk3128_cru *)devfdt_get_addr(dev);
This should be dev_read_addr ...
> + rkclk_init(priv->cru);
> +
> + return 0;
> +}
> +
> +static int rk3128_clk_bind(struct udevice *dev)
> +{
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(gd->dm_root, "rk3128_sysreset", "reset", &dev);
This will need to be updated to work with the master.
> + if (ret)
> + debug("Warning: No RK3128 reset driver: ret=%d\n", ret);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id rk3128_clk_ids[] = {
> + { .compatible = "rockchip,rk3128-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3128_cru) = {
> + .name = "clk_rk3128",
> + .id = UCLASS_CLK,
> + .of_match = rk3128_clk_ids,
> + .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
> + .ops = &rk3128_clk_ops,
> + .bind = rk3128_clk_bind,
> + .probe = rk3128_clk_probe,
> +};
>
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