[U-Boot] [U-BOOT][PATCH V3] sunxi: Use clrsetbits_le32 instead of multiple instruction

[Shyam Saini]

Please ignore this patch,

I have sent this patch as a part of original series.

Sorry for the noise.

Thanks and regards,
Shyam

On Fri, Mar 15, 2019 at 3:27 PM Shyam Saini
<shyam.saini at amarulasolutions.com> wrote:
>
> From: Michael Trimarchi <michael at amarulasolutions.com>
>
> This will improve code readabilty
>
> Signed-off-by: Michael Trimarchi <michael at amarulasolutions.com>
> ---
> Changelogs:
>            V1->V2: None
>            V2->V3: Fix use of clrsetbits_le32 and setbits_le32 functions
> ---
>  arch/arm/mach-sunxi/dram_sun8i_a33.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> index 1da2727f9874..09742cbc2b55 100644
> --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
> +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> @@ -148,11 +148,8 @@ static void auto_set_timing_para(struct dram_para *para)
>         reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
>         writel(reg_val, &mctl_ctl->dramtmg5);
>         /* Set two rank timing and exit self-refresh timing */
> -       reg_val = readl(&mctl_ctl->dramtmg8);
> -       reg_val &= ~(0xff << 8);
> -       reg_val &= ~(0xff << 0);
> -       reg_val |= (0x33 << 8);
> -       reg_val |= (0x8 << 0);
> +       clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0));
> +       setbits_le32(&mctl_ctl->dramtmg8, (0x33 << 8) | (0x8 << 0));
>         writel(reg_val, &mctl_ctl->dramtmg8);
>         /* Set phy interface time */
>         reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
> --
> 2.11.0
>