u-boot crash on T2080RDB_SPIFLASH

Chris Packham judge.packham at gmail.com
Wed Sep 2 07:22:40 CEST 2020


Hi,

Just tried out v2020.10-rc3 on my T2080RDB and I've got the following
splat. Haven't had a chance to decode it yet (pointers on how to
translate the addresses for powerpc welcome) but I figured I'd get
this out just in case anyone was looking at the T2080RDB.

SPI boot...
Initializing....using SPD
2 GiB left unmapped
Loading second stage boot loader
.................................................................................................

U-Boot 2020.10-rc3-00052-g502f0489f125 (Sep 02 2020 - 16:58:30 +1200)

CPU0:  T2080E, Version: 1.1, (0x85380011)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1799.820 MHz, CPU1:1799.820 MHz, CPU2:1799.820 MHz,
CPU3:1799.820 MHz,
       CCB:599.940 MHz,
       DDR:933.310 MHz (1866.620 MT/s data rate) (Asynchronous), IFC:599.940 MHz
       FMAN1: 699.930 MHz
       QMAN:  299.970 MHz
       PME:   599.940 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 1207001b 15000000 00000000 00000000
       00000010: 66150002 00000000 58104000 c1000000
       00000020: 00800000 00000000 00000000 000307fc
       00000030: 00000000 00000000 00000000 00000004
Model: fsl,T2080RDB
Board: T2080RDB, Board rev: 0x01 CPLD ver: 0x03, boot from SPI
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
SD2_CLK1=100.00MHZ, SD2_CLK2=100.00MHZ
DRAM:  Detected UDIMM D3XP56082XL10AA
2 GiB left unmapped
2 GiB (DDR3, 64-bit, CL=13, ECC on)
       DDR Chip-Select Interleaving Mode: CS0+CS1
VID: Could not find voltage regulator on I2C.
Warning: Adjusting core voltage failed.
Flash: 128 MiB
L2:    2 MiB enabled
Corenet Platform Cache: 512 KiB enabled
Using SERDES1 Protocol: 102 (0x66)
Using SERDES2 Protocol: 21 (0x15)
WARN: pls set popts->cpo_sample = 0x54 in <board>/ddr.c to optimize cpo
SEC0:  RNG instantiated
MMC:   FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected n25q512ax3 with page
size 256 Bytes, erase size 4 KiB, total 64 MiB
Bad trap at PC: 7ff7c9ec, SR: 21200, vector=d00
NIP: 7FF7C9EC XER: 00000000 LR: 7FF4942C REGS: 7fb2c8b0 TRAP: 0d00 DAR: FFFC9004
MSR: 00021200 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 7FF49570 7FB2C9A0 7FB2DE80 00000000 7FB2DEFC 00000020 7FB2CB04 7FFB1B64
GPR08: 00000008 FFFC9004 00000001 7FB2CB20 42002004 00000000 00000003 7FF9F738
GPR16: 7FB2CB90 7FB2CB78 00000000 7FB2CB68 00000000 00000800 7FB30B58 00000000
GPR24: 00000000 00000C94 7FB2DEFC 7FF9C695 00000000 00000020 7FFABA14 7FB337F8
Call backtrace:
00000000 7FF49570 7FF7D714 7FF8BE58 7FF8C8B8 7FF7C6FC 7FF7D8C4
7FF7CA88 7FF4C59C 7FF4C864 7FF31040
Exception in kernel pc 7ff7c9ec signal 0
### ERROR ### Please RESET the board ###


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