[PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h

[Pali Rohár]

Code for changing BootROM source is platform generic and can be used by any
P1* and P2* compatible board. Not only by RDB boards which use config
header file p1_p2_rdb_pc.h.

So move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.

This allows to use code for changing BootROM source also by other boards in
future.

Signed-off-by: Pali Rohár <pali at kernel.org>
---
 include/configs/p1_p2_bootrom.h | 32 +++++++++++++++
 include/configs/p1_p2_rdb_pc.h  | 73 +++++++++++++++++++++------------
 2 files changed, 78 insertions(+), 27 deletions(-)
 create mode 100644 include/configs/p1_p2_bootrom.h

diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h
new file mode 100644
index 000000000000..a1f61b788cf7
--- /dev/null
+++ b/include/configs/p1_p2_bootrom.h
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2022 Pali Rohár <pali at kernel.org>
+
+#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1
+
+#ifdef __SW_NOR_BANK_LO
+#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_NOR_BANK_UP
+#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_BOOT_NOR
+#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SPI
+#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SD
+#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_NAND
+#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_PCIE
+#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)
+#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 995bd983cef1..d41b31081017 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -79,6 +79,8 @@
  */
 #endif
 
+#include "p1_p2_bootrom.h"
+
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
@@ -575,30 +577,46 @@
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
 
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD	\
-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD
+#define __MAP_NOR_LOWER_CMD "map_lowernorbank="__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_LOWER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD
+#define __MAP_NOR_UPPER_CMD "map_uppernorbank="__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_UPPER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD
+#define __NOR_RST_CMD "norboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD	\
-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD
+#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0"
+#else
+#define __SPI_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD	\
-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD
+#define __SD_RST_CMD "sdboot="__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)"; reset\0"
+#else
+#define __SD_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD	\
-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD
+#define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0"
+#else
+#define __NAND_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD	\
-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD
+#define __PCIE_RST_CMD "pciboot="__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)"; reset\0"
+#else
+#define __PCIE_RST_CMD ""
 #endif
 
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
@@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 "nandfdtaddr=80000\0"		\
 "ramdisk_size=120000\0"	\
 __VSCFW_ADDR	\
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
-__stringify(__NOR_RST_CMD)"\0" \
-__stringify(__SPI_RST_CMD)"\0" \
-__stringify(__SD_RST_CMD)"\0" \
-__stringify(__NAND_RST_CMD)"\0" \
-__stringify(__PCIE_RST_CMD)"\0"
+__MAP_NOR_LOWER_CMD	\
+__MAP_NOR_UPPER_CMD	\
+__NOR_RST_CMD	\
+__SPI_RST_CMD	\
+__SD_RST_CMD	\
+__NAND_RST_CMD	\
+__PCIE_RST_CMD	\
+""
 
 #define CONFIG_USB_FAT_BOOT	\
 "setenv bootargs root=/dev/ram rw "	\
-- 
2.20.1