[PATCH V3 1/2] spi: cadence_qspi: setup ADDR Bits in cmd reads

[Pratyush Yadav]

On 25/11/22 11:29AM, Dhruva Gole wrote:
> Setup the Addr bit field while issuing register reads in STIG mode. This
> is needed for example flashes like cypress define in their transaction
> table that to read any register there is 1 cmd byte and a few more address
> bytes trailing the cmd byte. Absence of addr bytes will obviously fail
> to read correct data from flash register that maybe requested by flash
> driver because the controller doesn't even specify which address of the
> flash register the read is being requested from.
> 
> Signed-off-by: Dhruva Gole <d-gole at ti.com>

Reviewed-by: Pratyush Yadav <pratyush at kernel.org>

-- 
Regards,
Pratyush Yadav