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<DIV><FONT face=Arial size=2>I am just porting u-boot to our TOP860 module,
which uses 50MHz/80Mhz core clock and 25MHz/40MHz Bus Clock
(EBDF=1).</FONT></DIV>
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<DIV><FONT face=Arial size=2>I noticed that in cpu_init.c/line 77ff the
PLPRCR is written before SCCR which will cause the CLKOUT to ramp up to 50 MHz
before it is being reduced to half the frequency. That might violate alot of
timings. It does not appear to cause any problems right now; but I would suggest
anyway to change the order there.</FONT></DIV>
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<DIV><FONT face=Arial size=2>Regards Reinhard</FONT></DIV>
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