/*----------------------------------------------------------------------------- */
/* Function:     da_initdram */
/*----------------------------------------------------------------------------- */
        .globl  da_initdram
da_initdram:

	mflr	r31

        //-------------------------------------------------------------------
        // Set SDTR1
        //-------------------------------------------------------------------
        addi    r4,0,mem_sdtr1
        mtdcr   memcfga,r4
        addis   r4,0,0x0086		// PION Value for SDTR1
        ori     r4,r4,0x400D
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Set MB0CF
        //-------------------------------------------------------------------
        addi    r4,0,mem_mb0cf
        mtdcr   memcfga,r4
        addis   r4,0,0x0006		// PION Value for MB0CF
        ori     r4,r4,0x1001
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Set MB1CF
        //-------------------------------------------------------------------
        addi    r4,0,mem_mb1cf
        mtdcr   memcfga,r4
        addis   r4,0,0x0206		// PION Value for MB2CF
        ori     r4,r4,0x1001
        mtdcr   memcfgd,r4

	//-------------------------------------------------------------------
        // Set RTR
        //-------------------------------------------------------------------
        addi    r4,0,mem_rtr
        mtdcr   memcfga,r4
        addis   r4,0,0x0618		// PION Value for RTR
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Set memory controller options Reg.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        //addis   r4,0,0x00e0		// PION Value for MCOPT1
        addis   r4,0,0x80e0		// PION Value for MCOPT1
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Delay to ensure 200usec have elapsed since reset. Assume worst
        // case that the core is running 200Mhz:
        //   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
        //-------------------------------------------------------------------
        addis   r3,0,0x0000
        ori     r3,r3,0xA000          // ensure 200usec have passed since reset
        mtctr   r3
..spinlp2:
        bdnz    ..spinlp2               // spin loop

        //-------------------------------------------------------------------
        // Set memory controller options reg, MCOPT1.
	// Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
	// read/prefetch.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        addis   r4,0,0x80E0             // set DC_EN=1
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Delay to ensure 10msec have elapsed since reset. This is
        // required for the MPC952 to stabalize. Assume worst
        // case that the core is running 200Mhz:
        //   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
        // This delay should occur before accessing SDRAM.
        //-------------------------------------------------------------------
        addis   r3,0,0x001E
        ori     r3,r3,0x8480          // ensure 10msec have passed since reset
        mtctr   r3
..spinlp3:
        bdnz    ..spinlp3                // spin loop

        mtlr    r31                     // restore lr
        blr