Cleaned up PCI patch for MPC8266ADS board (Andy Lowe, MontaVista software) Added CFG_PCI_* options to overide PCI memory map in cpu/mpc8260/pci.c (Rune Torgersen) Fixed memory init code so it correctly initalizes bank 0 if greater than 16MB (Rune Torgersen) Full changelog for original PCI patch: board/mpc8266ads/config.mk * Changed the text base from 0xfff00000 to 0xfe000000 in order to boot low from the flash with base address 0xfe000000. board/mpc8266ads/mpc8266ads.c * Changed the I/O pin configuration for PC9 and PC10 for use as FETHMDIO and FETHMDC. * Added code in board_pre_init() to initialize the PCI interrupt mask register. * Changed board_pre_init() to enable the external transceiver for COM2 as well as COM1. * Changed the code in initdram() so the resulting SDRAM configuration when using the standard 16MB DIMM shipped with the board more closely resembles the configuration recommended in the MPC8266ADS manual. The refresh rate was being set to a higher frequency than necessary. * Added a call to the routine to initialize the PCI host bridge. cpu/mpc8260/cpu.c * Changed the checkcpu() function so it can identify an MPC8266 CPU as well as an MPC8260 CPU. The routine is still incomplete since it doesn't cover all of the 825x/826x variants. cpu/mpc8260/pci.c * This file is a bit of a problem since the PCI memory map is hardcoded here in code common to all MPC8260 targets, but one memory map may not necessarily be appropriate for all targets. For now I just changed the hardcoded memory map to one that I like better. This probably broke the PM826 u-boot port. The memory map definition could be #ifdef'd for each board, or the memory map definition could be moved to the board configuration header file. My motivation here was to move the PCI I/O space from 0xA0000000 to 0xF4000000. Having all the I/O regions above 0xF0000000 allows Linux to efficiently map them all with one BAT register. * I also changed the line that modifies the SIUMCR so it just changes the bits for the local bus configuration rather than overwriting all of the bits. * I added a one second delay after the PCI bus reset is released before PCI configuration space is accessed. The previous delay was only 1ms. The board would machine check on the first configuration space access with only a 1ms delay. Someone else has already added a CONFIG_PCI_BOOTDELAY parameter for this same purpose, but that doesn't help as currently implemented because that delay loop occurs while our PCI bus is still being held in reset. I suppose an alternative would be to move the release of the PCI reset out of the pci init function to somewhere it would execute earlier so that the CONFIG_PCI_BOOTDELAY would work as intended. * Since the PCI resource allocation functions in u-boot don't currently differentiate between prefetchable and non-prefetchable memory resources, I changed the pci_set_region() call for the memory region to use the non-prefetchable memory window instead of the prefetchable window. A non-prefetchable window works for a prefetchable resource, but a prefetchable window does not work for a non-prefetchable resource. drivers/pci_indirect.c * Changed a conditional hack for the PM826 board to a conditional hack for all 8260 boards. The hack adds a sync instruction after the write to the PCI_CONF_ADDR register. I found that configuration reads were sometimes returning incorrect values without the sync. include/configs/MPC8266ADS.h * Added support for the mii command. * Changed the default Ethernet MAC configuration from half-duplex to full-duplex. I've found that a full-duplex MAC can generally communicate successfully over a half-duplex link, but a half-duplex MAC can't necessarily communicate over a full-duplex link. * Enabled the pci commands. * Changed the clock frequency from 66.666666MHz to 66MHz since the board ships with a 66.0000MHz crystal. * Added some INITRD and NFS environment variable definitions copied from the SBC8260 u-boot configuration file. * Undefined CONFIG_CLOCKS_IN_MHZ in order to make the clock frequencies passed in the board info structure compatible with the current Linux kernel. * Changed the HRCW and SIUMCR to enable the PCI bus and to boot low rather than boot high. This means that u-boot must be programmed at the base of flash rather than in the last megabyte. * Rearranged the memory map to put all of the I/O regions above 0xF0000000. The flash is at 0xfe000000 instead of 0xff800000. * Added chip select configurations for the EEPROM, ATM UNI, and the PCI interrupt controller.