diff -ruNb u-boot-original/Makefile u-boot-work/Makefile
--- u-boot-original/Makefile	2004-04-16 02:23:39.000000000 +0300
+++ u-boot-work/Makefile	2004-04-16 18:38:02.222732120 +0300
@@ -401,8 +401,18 @@
 		 }
 	@./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
 
+xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
+
+NETPHONE_V2_config \
 NETPHONE_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx netphone
+	@ >include/config.h
+	@[ -z "$(findstring NETPHONE_config,$@)" ] || \
+		 { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
 
 xtract_NETTA = $(subst _ISDN,,$(subst _config,,$1))
 
diff -ruNb u-boot-original/board/netphone/flash.c u-boot-work/board/netphone/flash.c
--- u-boot-original/board/netphone/flash.c	2004-04-15 21:22:42.000000000 +0300
+++ u-boot-work/board/netphone/flash.c	2004-04-16 18:38:02.448697768 +0300
@@ -41,6 +41,9 @@
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
+#if CONFIG_NETPHONE_VERSION == 2
+	unsigned long size1;
+#endif
 	int i;
 
 	/* Init: no FLASHes known */
@@ -82,6 +85,25 @@
 
 	flash_info[0].size = size;
 
+#if CONFIG_NETPHONE_VERSION == 2
+	size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
+
+	if (flash_info[1].flash_id == FLASH_UNKNOWN && size1 > 0) {
+		printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
+	memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
+
+	flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
+
+	size += size1;
+#endif
+
 	return (size);
 }
 
diff -ruNb u-boot-original/board/netphone/netphone.c u-boot-work/board/netphone/netphone.c
--- u-boot-original/board/netphone/netphone.c	2004-04-15 21:22:42.000000000 +0300
+++ u-boot-work/board/netphone/netphone.c	2004-04-16 18:38:02.449697616 +0300
@@ -1,5 +1,6 @@
 /*
  * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -61,7 +62,7 @@
 
 int checkboard(void)
 {
-	printf ("Intracom NetPhone\n");
+	printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
 	return (0);
 }
 
@@ -105,30 +106,30 @@
 #define BS_1110		0x0E000000
 #define BS_1111		0x0F000000
 
-#define A10_AAAA	0x00000000
-#define A10_AAA0	0x00200000
-#define A10_AAA1	0x00300000
-#define A10_000A	0x00800000
-#define A10_0000	0x00A00000
-#define A10_0001	0x00B00000
-#define A10_111A	0x00C00000
-#define A10_1110	0x00E00000
-#define A10_1111	0x00F00000
-
-#define RAS_0000	0x00000000
-#define RAS_0001	0x00040000
-#define RAS_1110	0x00080000
-#define RAS_1111	0x000C0000
-
-#define CAS_0000	0x00000000
-#define CAS_0001	0x00010000
-#define CAS_1110	0x00020000
-#define CAS_1111	0x00030000
-
-#define WE_0000		0x00000000
-#define WE_0001		0x00004000
-#define WE_1110		0x00008000
-#define WE_1111		0x0000C000
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
 
 #define GPL4_0000	0x00000000
 #define GPL4_0001	0x00001000
@@ -155,6 +156,31 @@
 
 #define LAST		0x00000001
 
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
 /* #define CAS_LATENCY	3  */
 #define CAS_LATENCY	2
 
@@ -270,6 +296,55 @@
 	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
 };
 
+#if CONFIG_NETPHONE_VERSION == 2
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+#endif
+
 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
 #define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
@@ -329,7 +404,7 @@
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
-	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
 
 	/*
 	 * Preliminary prescaler for refresh
@@ -384,17 +459,6 @@
 
 	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
 
-#if 0
-	printf("check 0\n");
-	check_ram(( 0 << 20), (2 << 20));
-	printf("check 16\n");
-	check_ram((16 << 20), (2 << 20));
-	printf("check 32\n");
-	check_ram((32 << 20), (2 << 20));
-	printf("check 48\n");
-	check_ram((48 << 20), (2 << 20));
-#endif
-
 	if (size == 0) {
 		printf("SIZE is zero: LOOP on 0\n");
 		for (;;) {
@@ -447,19 +511,30 @@
 #define PB_GP_OUTVAL	(_B(26) | _B(27) | _B(29) | _B(30))
 #define PB_SP_DIRVAL	0
 
+#if CONFIG_NETPHONE_VERSION == 1
 #define PC_GP_INMASK	_BW(12)
 #define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(13) | _BW(15))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PC_GP_INMASK	(_BW(13) | _BW(15))
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(12))
+#endif
 #define PC_SP_MASK	0
 #define PC_SOVAL	0
 #define PC_INTVAL	0
 #define PC_GP_OUTVAL	(_BW(10) | _BW(11))
 #define PC_SP_DIRVAL	0
 
+#if CONFIG_NETPHONE_VERSION == 1
 #define PE_GP_INMASK	_B(31)
 #define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PE_GP_INMASK	_BR(28, 31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27))
+#endif
 #define PE_SP_MASK	0
 #define PE_ODR_VAL	0
-#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
 #define PE_SP_DIRVAL	0
 
 int board_early_init_f(void)
@@ -470,17 +545,23 @@
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	/* NAND chip select */
+#if CONFIG_NETPHONE_VERSION == 1
 	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
 	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#elif CONFIG_NETPHONE_VERSION == 2
+	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
+	memctl->memc_mamr = 0;	/* all clear */
+#endif
 
 	/* DSP chip select */
 	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
 	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 
-	/* External register chip select */
-	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
-	memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
-
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_br4 &= ~BR_V;
+#endif
 	memctl->memc_br5 &= ~BR_V;
 	memctl->memc_br6 &= ~BR_V;
 	memctl->memc_br7 &= ~BR_V;
@@ -588,6 +669,13 @@
 {
 	int i;
 
+#if CONFIG_NETPHONE_VERSION == 2
+	/* assert peripheral reset */
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	for (i = 0; i < 10; i++)
+		udelay(1000);
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+#endif
 	reset_phys();
 
 	/* check in order to enable the local console */
diff -ruNb u-boot-original/board/netphone/phone_console.c u-boot-work/board/netphone/phone_console.c
--- u-boot-original/board/netphone/phone_console.c	2004-04-15 21:22:42.000000000 +0300
+++ u-boot-work/board/netphone/phone_console.c	2004-04-16 18:38:02.449697616 +0300
@@ -62,6 +62,7 @@
 #define KP_FORCE_DELAY_HZ	(CFG_HZ/2)	/* key was force pressed */
 #define KP_IDLE_DELAY_HZ	(CFG_HZ/2)	/* key was released and idle */
 
+#if CONFIG_NETPHONE_VERSION == 1
 #define KP_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
 #define KP_SPI_RXD_MASK	0x0008
 
@@ -70,6 +71,16 @@
 
 #define KP_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
 #define KP_SPI_CLK_MASK	0x0001
+#elif CONFIG_NETPHONE_VERSION == 2
+#define KP_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_RXD_MASK	0x00000008
+
+#define KP_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_TXD_MASK	0x00000004
+
+#define KP_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_CLK_MASK	0x00000002
+#endif
 
 #define KP_CS_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat)
 #define KP_CS_MASK	0x00000010
@@ -975,9 +986,19 @@
 
 	val = 0x80 | (row_mask & 0x7F);
 	(void)kp_data_transfer(val);
+#if CONFIG_NETPHONE_VERSION == 1
 	col_mask = kp_data_transfer(val) & 0x0F;
+#elif CONFIG_NETPHONE_VERSION == 2
+	col_mask = ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & 0x0f;
+	/* XXX FUCK FUCK FUCK FUCK FUCK!!!! */
+	col_mask = ((col_mask & 0x08) >> 3) |	/* BKBR1 */
+		   ((col_mask & 0x04) << 1) |	/* BKBR2 */
+		    (col_mask & 0x02) |		/* BKBR3 */
+		   ((col_mask & 0x01) << 2);	/* BKBR4 */
 
+#endif
 	/* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */
+
 	return col_mask;
 }
 
diff -ruNb u-boot-original/include/configs/NETPHONE.h u-boot-work/include/configs/NETPHONE.h
--- u-boot-original/include/configs/NETPHONE.h	2004-04-15 21:22:44.000000000 +0300
+++ u-boot-work/include/configs/NETPHONE.h	2004-04-16 19:00:31.264646576 +0300
@@ -29,6 +29,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
+#error Unsupported CONFIG_NETPHONE version
+#endif
+
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -46,6 +50,7 @@
 /* #define CONFIG_XIN		 10000000 */
 #define CONFIG_XIN		 50000000
 #define MPC8XX_HZ		120000000
+/* #define MPC8XX_HZ		 66666666 */
 
 #define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
 
@@ -174,6 +179,11 @@
 #endif
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
 #define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#if CONFIG_NETPHONE_VERSION == 2
+#define CFG_FLASH_BASE4		0x40080000
+#endif
+
+#define CFG_RESET_ADDRESS   0x80000000
 
 /*
  * For booting Linux, the board info and command line data
@@ -185,7 +195,11 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
+#if CONFIG_NETPHONE_VERSION == 1
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#elif CONFIG_NETPHONE_VERSION == 2
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#endif
 #define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
@@ -302,6 +316,10 @@
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  66666666
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 50MHz
 #endif
@@ -363,6 +381,16 @@
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 #define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
+#if CONFIG_NETPHONE_VERSION == 2
+
+#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
+
+#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#endif
+
 /*
  * BR3 and OR3 (SDRAM)
  *
@@ -454,11 +482,9 @@
 
 #define DSP_SIZE	0x00010000	/* 64K */
 #define NAND_SIZE	0x00010000	/* 64K */
-#define ER_SIZE		0x00010000	/* 64K */
 
 #define DSP_BASE	0xF1000000
 #define NAND_BASE	0xF1010000
-#define ER_BASE		0xF1020000
 
 /****************************************************************/
 
@@ -507,11 +533,23 @@
 		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
 	} while(0)
 
+#if CONFIG_NETPHONE_VERSION == 1
 #define NAND_WAIT_READY(nand) \
 	do { \
+		int _tries = 0; \
 		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
-			; \
+			if (++_tries > 100000) \
+				break; \
+	} while (0)
+#elif CONFIG_NETPHONE_VERSION == 2
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int _tries = 0; \
+		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
+			if (++_tries > 100000) \
+				break; \
 	} while (0)
+#endif
 
 #define WRITE_NAND_COMMAND(d, adr) \
 	do { \
@@ -533,7 +571,12 @@
 
 /*****************************************************************************/
 
+#if CONFIG_NETPHONE_VERSION == 1
 #define STATUS_LED_BIT		0x00000008		/* bit 28 */
+#elif CONFIG_NETPHONE_VERSION == 2
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+#endif
+
 #define STATUS_LED_PERIOD	(CFG_HZ / 2)
 #define STATUS_LED_STATE	STATUS_LED_BLINKING
 
@@ -566,6 +609,13 @@
 
 /***********************************************************************************************************
 
+ ----------------------------------------------------------------------------------------------
+
+   (V1) version 1 of the board
+   (V2) version 2 of the board
+
+ ----------------------------------------------------------------------------------------------
+
    Pin definitions:
 
  +------+----------------+--------+------------------------------------------------------------
@@ -585,20 +635,64 @@
  | PB30 | SPI_CLK        | Output | SPI Clock
  | PC10 | DISPA0         | Output | Display A0
  | PC11 | BACKLIGHT      | Output | Display backlit
- | PC12 | SPI2RXD        | Input  | 2nd SPI RXD
- | PC13 | SPI2TXD        | Output | 2nd SPI TXD
- | PC15 | SPI2CLK        | Output | 2nd SPI CLK
+ | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
+ |      | IO_RESET       | Output | (V2) General I/O reset
+ | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
+ |      | HOOK           | Input  | (V2) Hook input interrupt
+ | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
+ |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
  | PE17 | F_ALE          | Output | NAND F_ALE
  | PE18 | F_CLE          | Output | NAND F_CLE
  | PE20 | F_CE           | Output | NAND F_CE
- | PE24 | SPICS_SCOUT    | Output | Codec chip select
+ | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
+ |      | LED            | Output | (V2) LED
  | PE27 | SPICS_ER       | Output | External serial register CS
- | PE28 | LEDIO1         | Output | LED
- | PE29 | LEDIO2         | Output | LED hook for A (TA2)
- | PE30 | LEDIO3         | Output | LED hook for A (TA2)
- | PE31 | F_RY_BY        | Input  | NAND F_RY_BY
+ | PE28 | LEDIO1         | Output | (V1) LED
+ |      | BKBR1          | Input  | (V2) Keyboard input scan
+ | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR2          | Input  | (V2) Keyboard input scan
+ | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR3          | Input  | (V2) Keyboard input scan
+ | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
+ |      | BKBR4          | Input  | (V2) Keyboard input scan
  +------+----------------+--------+---------------------------------------------------
 
+ ----------------------------------------------------------------------------------------------
+
+   Serial register input:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    0 | BKBR1          | (V1) Keyboard input scan 
+ |    1 | BKBR3          | (V1) Keyboard input scan 
+ |    2 | BKBR4          | (V1) Keyboard input scan 
+ |    3 | BKBR2          | (V1) Keyboard input scan 
+ |    4 | HOOK           | (V1) Hook switch 
+ |    5 | BT_LINK        | (V1) Bluetooth link status
+ |    6 | HOST_WAKE      | (V1) Bluetooth host wake up
+ |    7 | OK_ETH         | (V1) Cisco inline power OK status
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register output:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    0 | KEY1           | Keyboard output scan 
+ |    1 | KEY2           | Keyboard output scan 
+ |    2 | KEY3           | Keyboard output scan 
+ |    3 | KEY4           | Keyboard output scan 
+ |    4 | KEY5           | Keyboard output scan 
+ |    5 | KEY6           | Keyboard output scan 
+ |    6 | KEY7           | Keyboard output scan 
+ |    7 | BT_WAKE        | Bluetooth wake up
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
  Chip selects:
 
  +------+----------------+------------------------------------------------------------
@@ -608,8 +702,11 @@
  | CS1  | CS_FLASH       | NAND flash
  | CS2  | CS_DSP         | DSP
  | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_FLASH2      | (V2) 2nd flash
  +------+----------------+------------------------------------------------------------
 
+ ----------------------------------------------------------------------------------------------
+
  Interrupts:
 
  +------+----------------+------------------------------------------------------------
@@ -621,6 +718,8 @@
  | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
  +------+----------------+------------------------------------------------------------
 
+ ----------------------------------------------------------------------------------------------
+
  Interrupts on PCMCIA pins:
 
  +------+----------------+------------------------------------------------------------
@@ -630,6 +729,8 @@
  | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
  | IP_A2| RMII1_MDINT    | PHY interrupt for #1
  | IP_A3| RMII2_MDINT    | PHY interrupt for #2
+ | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
+ | IP_A6| OK_ETH         | (V2) Cisco inline power OK
  +------+----------------+------------------------------------------------------------
 
 *************************************************************************************************/
@@ -691,4 +792,11 @@
 
 /*************************************************************************************************/
 
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
 #endif	/* __CONFIG_H */
diff -ruNb u-boot-original/include/configs/NETTA.h u-boot-work/include/configs/NETTA.h
--- u-boot-original/include/configs/NETTA.h	2004-04-15 21:22:44.000000000 +0300
+++ u-boot-work/include/configs/NETTA.h	2004-04-16 19:00:40.862187528 +0300
@@ -117,6 +117,7 @@
 				CFG_CMD_MII 	| \
 				CFG_CMD_PCMCIA	| CFG_CMD_IDE | CFG_CMD_FAT | \
 				CFG_CMD_DIAG    | \
+				CFG_CMD_NFS	| \
 				CFG_CMD_CDP	  \
 				)
 
@@ -742,4 +743,12 @@
 
 /*************************************************************************************************/
 
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+
 #endif	/* __CONFIG_H */