Index: u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h
===================================================================
RCS file: /cvsroot/u-boot/u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h,v
retrieving revision 1.11
diff -u -r1.11 AT91RM9200.h
--- u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h	4 Oct 2005 23:52:35 -0000	1.11
+++ u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h	10 Oct 2005 12:32:02 -0000
@@ -255,7 +255,7 @@
 #define AT91C_SMC2_WSEN			((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
 #define AT91C_SMC2_TDF			((unsigned int) 0xF <<  8) /* (SMC2) Data Float Time */
 #define AT91C_SMC2_BAT			((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
-#define AT91C_SMC2_DBW			((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
+#define AT91C_SMC2_DBW			((unsigned int) 0x3 << 13) /* (SMC2) Data Bus Width */
 #define AT91C_SMC2_DBW_16		((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
 #define AT91C_SMC2_DBW_8		((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
 #define AT91C_SMC2_DRP			((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
@@ -265,7 +265,7 @@
 #define AT91C_SMC2_ACSS_2_CYCLES	((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
 #define AT91C_SMC2_ACSS_3_CYCLES	((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
 #define AT91C_SMC2_RWSETUP		((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
-#define AT91C_SMC2_RWHOLD		((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
+#define AT91C_SMC2_RWHOLD		((unsigned int) 0x7 << 28) /* (SMC2) Read and Write Signal Hold Time */
 
 /******************************************************************************/
 /*           SOFTWARE API DEFINITION  FOR Power Management Controler          */