<br><font size=2 face="sans-serif">Hi,</font>
<br>
<br><font size=2 face="sans-serif">Our MPC8260 based customs board's flash
configuration is as follows</font>
<br>
<br><font size=2 face="sans-serif">Flash Bank Base
Address Make
Number of flashes
per chip size
Total size</font>
<br>
<br><font size=2 face="sans-serif">CS0
0xFE000000
M29W040B
2
0.5MB
1MB</font>
<br><font size=2 face="sans-serif">CS1
0xFE800000
AM29LV160BB
2
2MB
4MB</font>
<br>
<br>
<br>
<br><font size=2 face="sans-serif">My question is</font>
<br>
<br><font size=2 face="sans-serif">1. Is is mandatory that CS0 and CS1
to be contiguous?</font>
<br><font size=2 face="sans-serif">2. what should be the value of CFG_MAX_FLASH_BANKS?
2 or 4? </font>
<br><font size=2 face="sans-serif">3. If for a board, CS0 has "n1"
number of flash chips connected and CS1 has "n2" number of flash
chips connected, then what will be the suggested structure of flash driver?
I found that flash drivers for different board does not consider the number
of physical flash chips present in a board. </font>
<br><font size=2 face="sans-serif">4.Is there any reference board which
has multiple flash chips connected both to CS0 and CS1? </font>
<br><font size=2 face="sans-serif"><br>
Thanks,</font>
<br><font size=2 face="sans-serif">Batsayan Das<br>
</font>
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