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<DIV><SPAN class=541024311-21032006><FONT face=Arial><FONT size=2>Hello,<SPAN
class=344340414-21032006> </SPAN></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=541024311-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006></SPAN></FONT></FONT></SPAN> </DIV>
<DIV><SPAN class=541024311-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>I am currently using a TQM866 with a cpu clock of
133MHz and<EM> </EM>I have problems with the configuration of the
SDRAM.</SPAN></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=541024311-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>H</SPAN>ere attached there is the sdram_table<SPAN
class=344340414-21032006> </SPAN><SPAN class=344340414-21032006>from the
following file:</SPAN><SPAN
class=344340414-21032006> </SPAN></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=541024311-21032006><SPAN class=344340414-21032006><FONT
face=Arial size=2></FONT></SPAN></SPAN> </DIV>
<DIV><SPAN class=541024311-21032006><SPAN
class=344340414-21032006>/u-boot_1.0.0/board/siemens/CCM/ccm.c</SPAN></SPAN></DIV>
<DIV><FONT size=2><SPAN class=541024311-21032006><SPAN
class=344340414-21032006></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006></SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>#define _NOT_USED_
0xFFFFFFFF</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>const uint sdram_table[]
=<BR>{<BR>
/*<BR> * Single Read. (Offset 0
in UPMA RAM)<BR>
*/<BR> 0x1F0DFC04, 0xEFAFBC04,
0x1EAF7C04, 0xF1AFFC04,<BR>
0xEFBAFC00, 0x1FF5FC47, _NOT_USED_, _NOT_USED_, /* last
*/</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>
/*<BR> * Burst Read. (Offset 8
in UPMA RAM)<BR>
*/<BR> 0x1F0DFC04, 0xEFAFBC04,
0x1EAF7C04, 0xF0AFFC04,<BR>
0xF0AFFC00, 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, /* last
*/<BR> 0x1FF5FC47, _NOT_USED_,
_NOT_USED_, _NOT_USED_,<BR>
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_,</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>
/*<BR> * Single Write. (Offset
18 in UPMA RAM)<BR>
*/<BR> 0x1F0DFC04, 0xEEABBC00,
0x01B27C04, 0xFFFFFC04,<BR>
0x1FF5FC47, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* last
*/</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>
/*<BR> * Burst Write. (Offset 20
in UPMA RAM)<BR>
*/<BR> 0x1F0DFC04, 0xEEABBC00,
0x10A77C00, 0xF0AFFC00,<BR>
0xF0AFFC00, 0xE1BAFC04, 0xFFFFFC04, 0x1FF5FC47, /* last
*/<BR> _NOT_USED_, _NOT_USED_,
_NOT_USED_,
_NOT_USED_,</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>
/*<BR> * SDRAM Initialization
(offset 2C in UPMA RAM)<BR>
*<BR> * This is no UPM entry
point. The following definition
uses<BR> * the remaining space
to establish an
initialization<BR> * sequence,
which is executed by a RUN
command.<BR>
*<BR>
*/<BR> 0x1FF5FC34, 0xEFEABC34,
0x1FB57C35, _NOT_USED_, /* last
*/</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>
/*<BR> * Refresh (Offset
30 in UPMA RAM)<BR>
*/<BR> 0x1FFD7C84, 0xFFFFFC04,
0xFFFFFC04, 0xFFFFFC04,<BR>
0xFFFFFC84, 0xFFFFFC07, _NOT_USED_, _NOT_USED_, /* last
*/<BR> _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,<BR>
/*<BR> * Exception. (Offset 3c
in UPMA RAM)<BR>
*/<BR> 0xFFFFFC07, _NOT_USED_,
_NOT_USED_, _NOT_USED_, /* last
*/<BR>};</SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006></SPAN></FONT></FONT></SPAN></SPAN></SPAN></SPAN></FONT></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT size=+0><SPAN class=541024311-21032006><SPAN
class=344340414-21032006><SPAN class=541024311-21032006><SPAN
class=100160114-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006>W</SPAN>e have<SPAN class=344340414-21032006>
only</SPAN> the following<SPAN
class=344340414-21032006> custom </SPAN>connections:</FONT></FONT></SPAN></SPAN></DIV>
<DIV>
<DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006>RAS --> GPL2</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006>A10 --> GPL0</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006>CAS --> GPL3</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006>WE --> GPL1</SPAN></SPAN></FONT></DIV><FONT
face=Arial
size=2> </FONT></SPAN></SPAN></FONT></DIV></SPAN></SPAN></FONT><FONT
face=Arial size=2><SPAN class=541024311-21032006><SPAN
class=100160114-21032006></SPAN></SPAN></FONT></DIV>
<DIV><SPAN class=541024311-21032006><FONT face=Arial><FONT size=2>Freescale<SPAN
class=344340414-21032006> said that the</SPAN></FONT></FONT></SPAN><SPAN
class=541024311-21032006><FONT face=Arial><FONT size=2> SDRAM timing is
determined by patterns programmed by the user in the UPM (User Programmable
Machine). <BR>According to the SDRAM manufacturers specification the "Write
Recovery Time" tWR is 15ns minimum. <BR>In the current UPM
patterns <SPAN class=344340414-21032006><FONT color=#0000ff><FONT
color=#000000> they</FONT> </FONT></SPAN> see only one clock period
for tWR. The clock period can be determined as follows: <BR> This also
explains why the board works ok when the core frequency is reduced to 130MHz,
since this translates to a bus clock period of 15.38ns. <BR><SPAN
class=344340414-21032006>They asked </SPAN>to insert another clock period
in the UPM pattern for "Write Recovery Time".<SPAN
class=344340414-21032006><FONT
color=#0000ff> </FONT></SPAN></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=541024311-21032006><FONT face=Arial><FONT size=2><SPAN
class=344340414-21032006> </SPAN><SPAN
class=344340414-21032006> </SPAN></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=541024311-21032006><SPAN class=344340414-21032006>I would like
to know how to modify the table to introduce the modification suggested by
Freescale. </SPAN></SPAN></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=541024311-21032006></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006>Thanks in advance
for you support</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=541024311-21032006></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=541024311-21032006>Agostino
Sette</DIV></SPAN></FONT>
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