Hi,<br>I want to apply some simple tests on MPC855T and need to turn on both instruction- and data-cache. I have used the codes in cpu/mpc8xx/start.S(as follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do I have to enable the MMU first? If so, how? I have tried the code in linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while trying to write MSR_DR|MSR_IR to msr.
<br> <br>Any ideas? Thanks! <br><br>Qichen<br><br><br>/* ************** dcache_enable in start.S ************ */<br> .globl dcache_enable<br>dcache_enable:<br>#if 0<br> SYNC<br>#endif<br>#if 1<br> lis r3, 0x0400 /* Set cache mode with MMU off */
<br> mtspr MD_CTR, r3<br>#endif<br><br> lis r3, IDC_INVALL@h<br> mtspr DC_CST, r3<br>#if 0<br> lis r3, DC_SFWT@h<br> mtspr DC_CST, r3<br>#endif<br> lis r3, IDC_ENABLE@h<br> mtspr DC_CST, r3<br> blr<br><br>/* ************ turn_on_mmu in head_8xx.S *********** */
<br> bl initial_mmu<br><br>/* We now have the lower 8 Meg mapped into TLB entries, and the caches<br> * ready to work.<br> */<br><br>turn_on_mmu:<br> mfmsr r0<br> ori r0,r0,MSR_DR|MSR_IR<br> mtspr SRR1,r0<br>blr<br><br>initial_mmu:
<br> tlbia /* Invalidate all TLB entries */<br>#ifdef CONFIG_PIN_TLB<br> lis r8, MI_RSV4I@h<br> ori r8, r8, 0x1c00<br>#else<br> li r8, 0<br>#endif<br> mtspr MI_CTR, r8 /* Set instruction MMU control */<br><br>#ifdef CONFIG_PIN_TLB
<br> lis r10, (MD_RSV4I | MD_RESETVAL)@h<br> ori r10, r10, 0x1c00<br> mr r8, r10<br>#else<br> lis r10, MD_RESETVAL@h<br>#endif<br>#ifndef CONFIG_8xx_COPYBACK<br> oris r10, r10, MD_WTDEF@h<br>#endif<br> mtspr MD_CTR, r10 /* Set data TLB control */
<br><br> /* Now map the lower 8 Meg into the TLBs. For this quick hack,<br> * we can load the instruction and data TLB registers with the<br> * same values.<br> */<br> lis r8, KERNELBASE@h /* Create vaddr for TLB */<br>
ori r8, r8, MI_EVALID /* Mark it valid */<br> mtspr MI_EPN, r8<br> mtspr MD_EPN, r8<br> li r8, MI_PS8MEG /* Set 8M byte page */<br> ori r8, r8, MI_SVALID /* Make it valid */<br> mtspr MI_TWC, r8<br> mtspr MD_TWC, r8<br>
li r8, MI_BOOTINIT /* Create RPN for address 0 */<br> mtspr MI_RPN, r8 /* Store TLB entry */<br> mtspr MD_RPN, r8<br> lis r8, MI_Kp@h /* Set the protection mode */<br> mtspr MI_AP, r8<br> mtspr MD_AP, r8<br><br> /* Map another 8 MByte at the IMMR to get the processor
<br> * internal registers (among other things).<br> */<br>#ifdef CONFIG_PIN_TLB<br> addi r10, r10, 0x0100<br> mtspr MD_CTR, r10<br>#endif<br> mfspr r9, 638 /* Get current IMMR */<br> andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
<br><br> mr r8, r9 /* Create vaddr for TLB */<br> ori r8, r8, MD_EVALID /* Mark it valid */<br> mtspr MD_EPN, r8<br> li r8, MD_PS8MEG /* Set 8M byte page */<br> ori r8, r8, MD_SVALID /* Make it valid */<br> mtspr MD_TWC, r8
<br> mr r8, r9 /* Create paddr for TLB */<br> ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */<br> mtspr MD_RPN, r8<br><br>#ifdef CONFIG_PIN_TLB<br> /* Map two more 8M kernel data pages.<br> */<br> addi r10, r10, 0x0100
<br> mtspr MD_CTR, r10<br><br> lis r8, KERNELBASE@h /* Create vaddr for TLB */<br> addis r8, r8, 0x0080 /* Add 8M */<br> ori r8, r8, MI_EVALID /* Mark it valid */<br> mtspr MD_EPN, r8<br> li r9, MI_PS8MEG /* Set 8M byte page */
<br> ori r9, r9, MI_SVALID /* Make it valid */<br> mtspr MD_TWC, r9<br> li r11, MI_BOOTINIT /* Create RPN for address 0 */<br> addis r11, r11, 0x0080 /* Add 8M */<br> mtspr MD_RPN, r8<br><br> addis r8, r8, 0x0080 /* Add 8M */
<br> mtspr MD_EPN, r8<br> mtspr MD_TWC, r9<br> addis r11, r11, 0x0080 /* Add 8M */<br> mtspr MD_RPN, r8<br>#endif<br><br> /* Since the cache is enabled according to the information we<br> * just loaded into the TLB, invalidate and enable the caches here.
<br> * We should probably check/set other modes....later.<br> */<br> lis r8, IDC_INVALL@h<br> mtspr IC_CST, r8<br> mtspr DC_CST, r8<br> lis r8, IDC_ENABLE@h<br> mtspr IC_CST, r8<br>#ifdef CONFIG_8xx_COPYBACK<br> mtspr DC_CST, r8
<br>#else<br> /* For a debug option, I left this here to easily enable<br> * the write through cache mode<br> */<br> lis r8, DC_SFWT@h<br> mtspr DC_CST, r8<br> lis r8, IDC_ENABLE@h<br> mtspr DC_CST, r8<br>#endif<br> blr
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