hi,<br>-- Another option is to make sure you run your codewithout using any U-Boot services (and interrupts disabled) and disable DC before returning.<br><br>I did so, but still couldn't get D-Cache enabled. <br><br>
<br><div><span class="gmail_quote">On 8/24/06, <b class="gmail_sendername">Wolfgang Denk</b> <<a href="mailto:wd@denx.de">wd@denx.de</a>> wrote:</span><blockquote class="gmail_quote" style="margin-top: 0; margin-right: 0; margin-bottom: 0; margin-left: 0; margin-left: 0.80ex; border-left-color: #cccccc; border-left-width: 1px; border-left-style: solid; padding-left: 1ex">
In message <<a href="mailto:b4ebaa9d0608240455p26c28d4ey2ebf3768f986c8c2@mail.gmail.com">b4ebaa9d0608240455p26c28d4ey2ebf3768f986c8c2@mail.gmail.com</a>> you wrote:<br>><br>> I want to apply some simple tests on MPC855T and need to turn on both
<br>> instruction- and data-cache. I have used the codes in cpu/mpc8xx/start.S(as<br><br>Please read the README to understand why this is not so easy.<br><br>> follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do I
<br>> have to enable the MMU first? If so,<br><br>This is one option, but it may require lots of changes everywhere in<br>the 8xx drivers. Another option is to make sure you run your code<br>without using any U-Boot services (and interrupts disabled) and
<br>disable DC before returning.<br><br>> how? I have tried the code in<br>> linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while<br>> trying to write MSR_DR|MSR_IR to msr.<br><br>U-Boot is not Linux, so no big surprise...
<br><br>Best regards,<br><br>Wolfgang Denk<br><br>--<br>Software Engineering: Embedded and Realtime Systems, Embedded Linux<br>Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: <a href="mailto:wd@denx.de">wd@denx.de
</a><br>There are certain things men must do to remain men.<br> -- Kirk, "The Ultimate Computer", stardate 4929.4<br></blockquote></div><br>