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<P class=MsoNormal style="MARGIN: 0in 0in 0pt"><SPAN style="COLOR: black">Hi,<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></SPAN></P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt"><SPAN style="COLOR: black"> <o:p></o:p></SPAN></P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt"><SPAN style="COLOR: black">I am working on system, which has chip set same as what is there in sc520_cdp board.<o:p></o:p></SPAN></P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt"><SPAN style="COLOR: black">In sc520_cdp board, for memory initialization, to write to DRAM control register they are writing to addr 0x0fffef010, for DRAM timing control register addr 0x0fffef012 and for DRAM bank configuration register addr 0x0fffef014 is used. (In file cpu/i386/sc520_asm. S) <o:p></o:p></SPAN></P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt"><SPAN style="COLOR: black">But according MCH manual these registers are PCI registers and can be accessed via CONFIG</SPAN>_ADDRESS and CONFIG_DATA, located at I/O addr 0xCF8 and 0xCFC respectively.</P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt"><SPAN style="COLOR: black">Can anyone explain me, how actually in sc520_cdp board they˘re are using the addr 0x0fffef012 for DRAM register and so on.<o:p></o:p></SPAN></P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt"> <o:p></o:p></P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt">Thanks,</P>
<P class=MsoNormal style="MARGIN: 0in 0in 0pt">Mushtaq Khan</P></DIV></div><br>
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