diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index e5058a4..2b4b318 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -347,6 +347,11 @@
 #define MCFSDRAMC_DMR_V         (0x00000001)
 
 #define MCFWTM_WCR              (*(vu_short *)(CFG_MBAR+0x00140000))
+#define MCFWTM_WCR_EN			(0x0001)
+#define MCFWTM_WCR_HALTED		(0x0002)
+#define MCFWTM_WCR_DOZE			(0x0004)
+#define MCFWTM_WCR_WAIT			(0x0008)
+
 #define MCFWTM_WMR              (*(vu_short *)(CFG_MBAR+0x00140002))
 #define MCFWTM_WCNTR            (*(vu_short *)(CFG_MBAR+0x00140004))
 #define MCFWTM_WSR              (*(vu_short *)(CFG_MBAR+0x00140006))
@@ -376,6 +381,39 @@
 
 /*********************************************************************
 *
+* Inter-IC (I2C) Module
+*
+*********************************************************************/
+
+/* Read/Write access macros for general use */
+#define MCFI2C_I2ADR		(*(vu_char *)(CFG_MBAR+0x00000300))
+#define MCFI2C_I2FDR		(*(vu_char *)(CFG_MBAR+0x00000304))
+#define MCFI2C_I2CR			(*(vu_char *)(CFG_MBAR+0x00000308))
+#define MCFI2C_I2SR			(*(vu_char *)(CFG_MBAR+0x0000030C))
+#define MCFI2C_I2DR			(*(vu_char *)(CFG_MBAR+0x00000310))
+
+/* Bit level definitions and macros */
+#define MCFI2C_I2ADR_ADDR(x)		(((x)&0x7F)<<0x01)
+
+#define MCFI2C_I2FDR_IC(x)			(((x)&0x3F))
+
+#define MCFI2C_I2CR_IEN				(0x80)
+#define MCFI2C_I2CR_IIEN			(0x40)
+#define MCFI2C_I2CR_MSTA			(0x20)
+#define MCFI2C_I2CR_MTX				(0x10)
+#define MCFI2C_I2CR_TXAK			(0x08)
+#define MCFI2C_I2CR_RSTA			(0x04)
+
+#define MCFI2C_I2SR_ICF				(0x80)
+#define MCFI2C_I2SR_IAAS			(0x40)
+#define MCFI2C_I2SR_IBB				(0x20)
+#define MCFI2C_I2SR_IAL				(0x10)
+#define MCFI2C_I2SR_SRW				(0x04)
+#define MCFI2C_I2SR_IIF				(0x02)
+#define MCFI2C_I2SR_RXAK			(0x01)
+
+/*********************************************************************
+*
 * General Purpose Timer (GPT) Module
 *
 *********************************************************************/
@@ -541,5 +579,75 @@
 #define MCFCFM_CMD_PGERS		0x40
 #define MCFCFM_CMD_MASERS		0x41
 
+/*********************************************************************
+*
+* Interupt Controller (ICM) Module
+*
+*********************************************************************/
+
+#define MCFICM_IMRH0			(*(vu_long*) (CFG_MBAR+0x00000C08))
+#define MCFICM_IMRH0_FEC_GRA	0x00000001
+#define MCFICM_IMRH0_FEC_EBERR	0x00000002
+#define MCFICM_IMRH0_FEC_BABT	0x00000004
+#define MCFICM_IMRH0_FEC_BABR	0x00000008
+#define MCFICM_IMRH0_PMM		0x00000010
+#define MCFICM_IMRH0_QADC_CF1	0x00000020
+#define MCFICM_IMRH0_QADC_CF2	0x00000040
+#define MCFICM_IMRH0_QADC_PF1	0x00000080
+
+#define MCFICM_IMRH0_QADC_PF2	0x00000100
+#define MCFICM_IMRH0_GPTA_TOF	0x00000200
+#define MCFICM_IMRH0_GPTA_PAIF	0x00000400
+#define MCFICM_IMRH0_GPTA_PAOVF	0x00000800
+#define MCFICM_IMRH0_GPTA_C0F	0x00001000
+#define MCFICM_IMRH0_GPTA_C1F	0x00002000
+#define MCFICM_IMRH0_GPTA_C2F	0x00004000
+#define MCFICM_IMRH0_GPTA_C3F	0x00008000
+
+#define MCFICM_IMRH0_GPTB_TOF	0x00010000
+#define MCFICM_IMRH0_GPTB_PAIF	0x00020000
+#define MCFICM_IMRH0_GPTB_PAOVF	0x00040000
+#define MCFICM_IMRH0_GPTB_C0F	0x00080000
+#define MCFICM_IMRH0_GPTB_C1F	0x00100000
+#define MCFICM_IMRH0_GPTB_C2F	0x00200000
+#define MCFICM_IMRH0_GPTB_C3F	0x00400000
+#define MCFICM_IMRH0_PIT0		0x00800000
+
+#define MCFICM_IMRH0_PIT1		0x01000000
+#define MCFICM_IMRH0_PIT2		0x02000000
+#define MCFICM_IMRH0_PIT3		0x04000000
+#define MCFICM_IMRH0_CFM_CBEIF	0x08000000
+#define MCFICM_IMRH0_CFM_CCIF	0x10000000
+#define MCFICM_IMRH0_CFM_PVIF	0x20000000
+#define MCFICM_IMRH0_CFM_AEIF	0x40000000
+#define MCFICM_IMRH0_63			0x80000000
+
+#define MCFICM_ICR_IL		3
+#define MCFICM_ICR_IP		0
+
+#define MCFICM_ICR_PIT0		(*(vu_char*) (CFG_MBAR+0x00000C77))
+#define MCFICM_ICR_PIT1		(*(vu_char*) (CFG_MBAR+0x00000C78))
+#define MCFICM_ICR_PIT2		(*(vu_char*) (CFG_MBAR+0x00000C79))
+#define MCFICM_ICR_PIT3		(*(vu_char*) (CFG_MBAR+0x00000C7A))
+
+/*********************************************************************
+*
+* Vectors
+*
+*********************************************************************/
+
+#define MCFVECTOR_INTC0_OFFSET			64
+
+#define MCFVECTOR_UART0					MCFVECTOR_INTC0_OFFSET+13
+#define MCFVECTOR_UART1					MCFVECTOR_INTC0_OFFSET+14
+#define MCFVECTOR_UART2					MCFVECTOR_INTC0_OFFSET+15
+
+#define MCFVECTOR_I2C					MCFVECTOR_INTC0_OFFSET+17
+
+#define MCFVECTOR_PIT0					MCFVECTOR_INTC0_OFFSET+55
+#define MCFVECTOR_PIT1					MCFVECTOR_INTC0_OFFSET+56
+#define MCFVECTOR_PIT2					MCFVECTOR_INTC0_OFFSET+57
+#define MCFVECTOR_PIT3					MCFVECTOR_INTC0_OFFSET+58
+
 /****************************************************************************/
 #endif	/* m5282_h */