<DIV>Hi,</DIV>
<DIV> </DIV>
<DIV> I bring up the u-boot in my 440EPx based on board successfully, it work fine when I disable the ECC, however when I enable the ECC I found it work unstablely in u-boot, for example it sometimes crashed in 'tftp' download.</DIV>
<DIV> </DIV>
<DIV> Is there someone also encounter this issue?</DIV>
<DIV> </DIV>
<DIV>My code AS below:</DIV>
<DIV>long int sequoia_sdram_init (int board_type)<BR>{<BR>#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)<BR> u32 val = 0;<BR> ulong speed = get_bus_freq(0);</DIV>
<DIV> mtsdram(DDR0_02, 0x00000000);</DIV>
<DIV> mtsdram(DDR0_00, 0x0000190A);<BR> mtsdram(DDR0_01, 0x01000000);<BR> mtsdram(DDR0_03, 0x02030602); //CASLAT = 3, CLATLN = 3<BR> //mtsdram(DDR0_03, 0x02040802); //CASLAT = 4, CLATLN = 4</DIV>
<DIV> //mtsdram(DDR0_04, 0x0A020200);<BR> mtsdram(DDR0_04, 0x0C020200);</DIV>
<DIV> mtsdram(DDR0_05, 0x02020308);<BR> mtsdram(DDR0_06, 0x0102C812);<BR> mtsdram(DDR0_07, 0x000D0100);<BR> // mtsdram(DDR0_08, 0x02430001); //WR = 2 (far CAS 3)<BR> mtsdram(DDR0_08, 0x02C80001); //when in doubt set tcpd to 200cycles 08/28/07<BR> //mtsdram(DDR0_08, 0x03430001); //WR = 2 (far CAS 4)</DIV>
<DIV> //mtsdram(DDR0_09, 0x00011D5F); // 75ohm RTT</DIV>
<DIV> //mtsdram(DDR0_09, 0x00001D5F); // Termination disabled</DIV>
<DIV> /* for tuning WDS */<BR> //mtsdram(DDR0_09, 0x00011D50);<BR> //mtsdram(DDR0_09, 0x00011D4F);<BR> mtsdram(DDR0_09, 0x00011D40);</DIV>
<DIV> //mtsdram(DDR0_10, 0x00000300); // dual rank</DIV>
<DIV> mtsdram(DDR0_10, 0x00000100); // single rank</DIV>
<DIV> mtsdram(DDR0_11, 0x0027C800);<BR> mtsdram(DDR0_12, 0x00000003);<BR> //mtsdram(DDR0_14, 0x00000000);<BR> mtsdram(DDR0_14, 0x00000100);<BR> mtsdram(DDR0_17, 0x19000000);<BR> mtsdram(DDR0_18, 0x19191919);<BR> mtsdram(DDR0_19, 0x19191919);<BR> mtsdram(DDR0_20, 0x0B0B0B0B);<BR> mtsdram(DDR0_21, 0x0B0B0B0B);<BR> //mtsdram(DDR0_22, 0x00267F0B); // no ECC<BR> //mtsdram(DDR0_22, 0x03267F0B); // enable ECC</DIV>
<DIV> /* for tuning DQSOSH */<BR> //mtsdram(DDR0_22, 0x0026700B); // no ECC<BR> //mtsdram(DDR0_22, 0x03266F0B); // ECC<BR> mtsdram(DDR0_22, 0x0026600B); // ECC</DIV>
<DIV> mtsdram(DDR0_23, 0x00000000);<BR> //mtsdram(DDR0_24, 0x01010002); //ODT_WR_MAP_CS0 = <BR> mtsdram(DDR0_24, 0x01010001); //ODT_WR_MAP_CS0 = </DIV>
<DIV> printf("DDR Init: speed = %d \n", speed);<BR> if (speed > 133333334) {<BR> mtsdram(DDR0_26, 0x5B26050C);<BR> }<BR> else {<BR> mtsdram(DDR0_26, 0x5B260408);<BR> }</DIV>
<DIV> mtsdram(DDR0_27, 0x0000682B);<BR> mtsdram(DDR0_28, 0x00000000);<BR> mtsdram(DDR0_31, 0x00000000);<BR> //mtsdram(DDR0_42, 0x01000006);<BR> mtsdram(DDR0_42, 0x00000006);<BR> mtsdram(DDR0_43, 0x030A0200);<BR> mtsdram(DDR0_44, 0x00000003);<BR> mtsdram(DDR0_02, 0x00000001);</DIV>
<DIV> wait_for_dlllock();<BR>#endif /* #ifndef CONFIG_NAND_U_BOOT */</DIV>
<DIV>#ifdef CONFIG_DDR_DATA_EYE<BR> /* -----------------------------------------------------------+<BR> * Perform data eye search if requested.<BR> * ----------------------------------------------------------*/<BR> denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);<BR>#endif</DIV>
<DIV>#ifdef CONFIG_DDR_ECC</DIV>
<DIV>{<BR> unsigned long write_addr;<BR> unsigned long registerVal;<BR> unsigned long memory_size = (CFG_MBYTES_SDRAM << 20);</DIV>
<DIV> /* 0- Enable ECC */<BR> mtdcr(ddrcfga, DDR0_22);<BR> registerVal = mfdcr(ddrcfgd);<BR> registerVal = (registerVal &~ DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_ENABLE;<BR> mtdcr(ddrcfgd, registerVal);</DIV>
<DIV> /* 1- Clear entire memory content */<BR> write_addr = CFG_SDRAM_BASE;<BR> printf("ECC Enabling\n");<BR> printf("Start memory clearing @ 0x%08x size = 0x%08x...", write_addr, memory_size);<BR> while (write_addr < memory_size) {<BR> *((unsigned long*)write_addr) = write_addr;<BR> write_addr += 8;<BR>#ifdef DDR_DEBUG_SIZE<BR> if ( (write_addr % 0x10000000 ) == 0)<BR> printf("addr = 0x%08x \n", write_addr );<BR>#endif<BR> }<BR> printf(" DONE\n");</DIV>
<DIV> /* 2- Clear error status */<BR> mtdcr(ddrcfga, DDR0_00);<BR> registerVal = mfdcr(ddrcfgd);<BR> mtdcr(ddrcfgd, (registerVal | DDR0_00_INT_ACK_ALL));</DIV>
<DIV> /* 3- Set 'int_mask' parameter to functionnal value */<BR> #ifdef DDR_DEBUG<BR> printf("Set 'int_mask' parameter to functionnal value\n");<BR> #endif<BR> mtdcr(ddrcfga, DDR0_01);<BR> registerVal = mfdcr(ddrcfgd);</DIV>
<DIV> mtdcr(ddrcfgd, ((registerVal &~ DDR0_01_INT_MASK_MASK)<BR> | DDR0_01_INT_MASK_ALL_OFF));<BR>}<BR>#endif</DIV>
<DIV> mtdcr(ddrcfga, DDR0_02);<BR> val = mfdcr(ddrcfgd);</DIV>
<DIV> //dump_ddr2_regs();</DIV>
<DIV> return (CFG_MBYTES_SDRAM << 20);<BR>}</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>- Denny</DIV>
<DIV> </DIV>
<DIV ></DIV><BR><br><!-- footer --><br>
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