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<DIV>thank you. you are right.</DIV>
<DIV>I find the reason in the manual: </DIV>
<DIV>DCE 2 Data cache enable<BR>0 The data cache is neither accessed nor
updated. All pages are accessed as if they were<BR>marked cache-inhibited (WIM =
x1x). Potential cache accesses from the bus (snoop and cache<BR>operations) are
ignored. In the disabled state for the L1 caches, the cache tag state bits
are<BR>ignored and all accesses are propagated to the L2 cache, L3 cache, or bus
as cache-inhibited.<BR>For those transactions, CI is asserted regardless of
address translation.DCE is zero at<BR>power-up.<BR>1 The data cache is
enabled.Note that HID0[DCFI] must be set at the same time that this bit is
set.</DIV>
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<DIV>-------------------------</DIV>
<DIV>Most likely neither are redundant. To say for sure, you need to read
<BR>the User's Manual for the 74xx family where it specifies how to change
<BR>the HID0 register</DIV>
<DIV>....................</DIV>
<DIV> </DIV>
<DIV>HTH,<BR>gvb</DIV></BODY></HTML>