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Hi Shinya,<BR>
<BR>
Thanks for your support and your code patches.<BR>
I'm waiting for a Lauterbach trace32 to debug deeply the code and understand better the behaviour.<BR>
I'll send you my feedback next week.<BR>
<BR>
Best regards,<BR>
<BR>
luigi<BR>
<BR>
<BR>
On sab, 2008-02-16 at 18:06 +0900, Shinya Kuribayashi wrote:
<BLOCKQUOTE TYPE=CITE>
<PRE>
<FONT COLOR="#000000">Shinya Kuribayashi wrote:</FONT>
<FONT COLOR="#000000">> Shinya Kuribayashi wrote:</FONT>
<FONT COLOR="#000000">>>> I think that on my application the UNCACHED_SDRAM should map the address</FONT>
<FONT COLOR="#000000">>>> on KSEG1 (how it is now) but this simply doesn't work. Instead, using</FONT>
<FONT COLOR="#000000">>>> the PHYSADDR(a) macro... the kernel is able to start.</FONT>
<FONT COLOR="#000000">>>></FONT>
<FONT COLOR="#000000">>>> I suspect that there are issues on cache management. Can be? </FONT>
<FONT COLOR="#000000">>> IMHO it's not related to cache.</FONT>
<FONT COLOR="#000000">> </FONT>
<FONT COLOR="#000000">> How do you set ERL and EXL bits? Please try to clear them at the</FONT>
<FONT COLOR="#000000">> STATUS register initialization like:</FONT>
<FONT COLOR="#000000">> </FONT>
<FONT COLOR="#000000">> reset:</FONT>
<FONT COLOR="#000000">> <snip></FONT>
<FONT COLOR="#000000">> </FONT>
<FONT COLOR="#000000">> /* STATUS register */</FONT>
<FONT COLOR="#000000">> mfc0 k0, CP0_STATUS</FONT>
<FONT COLOR="#000000">> - li k1, ~ST0_IE</FONT>
<FONT COLOR="#000000">> + li k1, ~(ST0_ERL | ST0_EXL | ST0_IE)</FONT>
<FONT COLOR="#000000">> and k0, k1</FONT>
<FONT COLOR="#000000">> mtc0 k0, CP0_STATUS</FONT>
<FONT COLOR="#000000">> </FONT>
<FONT COLOR="#000000">> ERL and EXL disable exceptions. Due to this spec, we are in danger</FONT>
<FONT COLOR="#000000">> of overlooking something critical. If this change brings in new</FONT>
<FONT COLOR="#000000">> exception(s), please fix the causes of them first. Hope this helps.</FONT>
<FONT COLOR="#000000">Err, sorry for confusing example. Here's the right one:</FONT>
<FONT COLOR="#000000">diff --git a/cpu/mips/start.S b/cpu/mips/start.S</FONT>
<FONT COLOR="#000000">index c92b162..02797f7 100644</FONT>
<FONT COLOR="#000000">--- a/cpu/mips/start.S</FONT>
<FONT COLOR="#000000">+++ b/cpu/mips/start.S</FONT>
<FONT COLOR="#000000">@@ -211,14 +211,20 @@ reset:</FONT>
<FONT COLOR="#000000"> mtc0 zero, CP0_WATCHLO</FONT>
<FONT COLOR="#000000"> mtc0 zero, CP0_WATCHHI</FONT>
<FONT COLOR="#000000"> </FONT>
<FONT COLOR="#000000">+ /* Inhibit deffered WATCH exception */</FONT>
<FONT COLOR="#000000">+ mfc0 k0, CP0_CAUSE</FONT>
<FONT COLOR="#000000">+ li k1, ~(1UL << 22) # CP0.Cause.WP = 0</FONT>
<FONT COLOR="#000000">+ and k0, k0, k1</FONT>
<FONT COLOR="#000000">+ mtc0 k0, CP0_CAUSE</FONT>
<FONT COLOR="#000000">+</FONT>
<FONT COLOR="#000000"> /* STATUS register */</FONT>
<FONT COLOR="#000000"> #ifdef CONFIG_TB0229</FONT>
<FONT COLOR="#000000"> li k0, ST0_CU0</FONT>
<FONT COLOR="#000000"> #else</FONT>
<FONT COLOR="#000000"> mfc0 k0, CP0_STATUS</FONT>
<FONT COLOR="#000000"> #endif</FONT>
<FONT COLOR="#000000">- li k1, ~ST0_IE</FONT>
<FONT COLOR="#000000">- and k0, k1</FONT>
<FONT COLOR="#000000">+ ori k0, (ST0_ERL | ST0_EXL | ST0_IE)</FONT>
<FONT COLOR="#000000">+ xori k0, (ST0_ERL | ST0_EXL)</FONT>
<FONT COLOR="#000000"> mtc0 k0, CP0_STATUS</FONT>
<FONT COLOR="#000000"> </FONT>
<FONT COLOR="#000000"> /* CAUSE register */</FONT>
<FONT COLOR="#000000">Again, it's highy recommended to make sure U-Boot works fine under</FONT>
<FONT COLOR="#000000">interrupts enabled (CP0.Status.IE=1), before digging into UNCACHED_</FONT>
<FONT COLOR="#000000">SDRAM problem.</FONT>
<FONT COLOR="#000000"> Shinya</FONT>
</PRE>
</BLOCKQUOTE>
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<B>Luigi Mantellini</B><BR>
R&D - Software<BR>
<TT>Industrie Dial Face S.p.A.</TT><BR>
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