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<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008>Hi
,</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=261510015-12032008></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>We are using U-Boot-1.1.3 on a custom
MPC8349ADS board with 2 PCI buses configured in Host mode.We have 256 MB
DDR2 in our board.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>We have connected 8 DSPs on PCI bus
1.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>U-Boot is assigning base address for DSPs from
0x80000000 to 0x93800000.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>We are able to access any location from 0x80000000 to
0x0x8FFFFFFF i.e first 256 MB using md command in
U-BOOT.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>But when i try to access any location starting from
0x90000000 to 0x93800000(next 256 MB)</SPAN></SPAN></FONT><FONT face=Arial
size=2><SPAN class=261510015-12032008><SPAN class=435590206-13032008>,
<STRONG>U-Boot hangs :</STRONG></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG>=>md 0x90000000
</STRONG></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG>90000000: </STRONG></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>Even though PCI LAWBARs and Outbound window is
configured for 512 MB starting from 0x80000000.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>I am not able to understand why i am not able to access
any location starting from 0x90000000.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>Please help me in as i have already wasted too much
time in debugging this issue.</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>I am also attaching the U-Boot PCI
settings:</SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG>We are Configuring PCI bus in Host mode
with following settings:</STRONG></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>/* PCI window setting in
include/configs/MPC8349ADS.h start */<BR>#define
CFG_PCI1_MEM_BASE 0x80000000<BR>#define
CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE<BR>#define
CFG_PCI1_MEM_SIZE 0x20000000 /* 512M
*/</SPAN></SPAN></FONT></DIV><FONT><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>
<DIV><FONT face=Arial size=2></FONT><FONT face=Arial size=2></FONT><FONT
face=Arial size=2></FONT><FONT face=Arial size=2></FONT><BR><FONT face=Arial
size=2>#define CFG_PCI1_IO_BASE 0x00000000<BR>#define
CFG_PCI1_IO_PHYS 0xe2000000<BR>#define CFG_PCI1_IO_SIZE 0x<SPAN
class=435590206-13032008>0</SPAN>1000000 /* 16M */</FONT></DIV>
<DIV><SPAN class=261510015-12032008><SPAN class=435590206-13032008><FONT
face=Arial size=2>/* PCI window setting in MPC8349ADS.h
start */</FONT></SPAN></SPAN></DIV><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></SPAN></SPAN></FONT></DIV><FONT
face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG><U>PCI LAWBARas
setting:</U></STRONG></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG><U></U></STRONG></SPAN></SPAN></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>/* PCI LAWBARs setting in cpu/83xx/pci.c :
start*/</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> pci_law[0].bar = CFG_PCI1_MEM_PHYS &
LAWBAR_BAR; /* base: 0x80000000 */<BR> pci_law[0].ar = LAWAR_EN |
LAWAR_SIZE_1G;</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> pci_law[1].bar = CFG_PCI1_IO_PHYS &
LAWBAR_BAR; /* base: 0xe2000000 */<BR> pci_law[1].ar = LAWAR_EN |
LAWAR_SIZE_16M;</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>/* PCI LAWBARs setting in cpu/83xx/pci.c
:end*/</SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG><U>PCI Outbound translation register
setting:</U></STRONG></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> /* PCI1 mem space
*/<BR> pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) &
POTAR_TA_MASK;
/* base: 0x80000000 */<BR> pci_pot[0].pobar =
(CFG_PCI1_MEM_PHYS >> 12) &
POBAR_BA_MASK;
/* base: 0x80000000 */<BR> pci_pot[0].pocmr = POCMR_EN |
(<STRONG>POCMR_CM_512M</STRONG> & POCMR_CM_MASK);
</SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> /* PCI1 IO space */<BR> pci_pot[1].potar =
(CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;<BR> pci_pot[1].pobar =
(CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;<BR> pci_pot[1].pocmr =
POCMR_EN | POCMR_IO | (POCMR_CM_16M &
POCMR_CM_MASK);<BR></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>/*<BR> * Configure PCI Inbound Translation
Windows<BR> */</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> /* we need RAM mapped to PCI space for the
devices to<BR> * access main memory */<BR> pci_ctrl[0].pitar1 =
0x0;<BR> pci_ctrl[0].pibar1 = 0x0;<BR> pci_ctrl[0].piebar1 =
0x0;<BR> pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) -
1);<BR></SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> hose->first_busno =
0;<BR> hose->last_busno = 0xff;</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><STRONG> /* PCI memory space
*/<BR> pci_set_region(hose->regions +
0,<BR>
CFG_PCI1_MEM_BASE, </STRONG> /* base:
0x80000000 */<BR><STRONG>
CFG_PCI1_MEM_PHYS,<BR>
CFG_PCI1_MEM_SIZE,</STRONG> <STRONG>
</STRONG> /* Size is 512 MB
*/<BR><STRONG>
PCI_REGION_MEM);</STRONG> </SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> /* PCI IO space
*/<BR> pci_set_region(hose->regions +
1,<BR>
CFG_PCI1_IO_BASE,<BR>
CFG_PCI1_IO_PHYS,<BR>
CFG_PCI1_IO_SIZE,<BR>
PCI_REGION_IO);</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> /* System memory space
*/<BR> pci_set_region(hose->regions +
2,<BR>
CONFIG_PCI_SYS_MEM_BUS,<BR>
CONFIG_PCI_SYS_MEM_PHYS,<BR>
gd->ram_size, <BR>
PCI_REGION_MEM | PCI_REGION_MEMORY);</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> hose->region_count =
3;</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><BR> pci_setup_indirect(hose,<BR>
(CFG_IMMRBAR+0x8300),<BR>
(CFG_IMMRBAR+0x8304));</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> pci_register_hose(hose);</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008> /*<BR> * Write to Command
register<BR> */<BR> reg16 = 0xff;<BR> dev =
PCI_BDF(hose->first_busno, 0, 0);<BR> pci_hose_read_config_word (hose,
dev, PCI_COMMAND, &reg16);<BR> reg16 |= PCI_COMMAND_SERR |
PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY;<BR> pci_hose_write_config_word(hose, dev, PCI_COMMAND,
reg16);</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><BR> /*<BR> * Clear non-reserved bits in
status register.<BR> */<BR> pci_hose_write_config_word(hose, dev,
PCI_STATUS, 0xffff);<BR> pci_hose_write_config_byte(hose, dev,
PCI_LATENCY_TIMER, 0x80);<BR> pci_hose_write_config_byte(hose, dev,
PCI_CACHE_LINE_SIZE, 0x08);</SPAN></SPAN></SPAN></SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008><SPAN class=261510015-12032008><SPAN
class=435590206-13032008>#ifdef
CONFIG_PCI_SCAN_SHOW<BR> printf("PCI: Bus Dev VenId DevId Class
Int\n");<BR>#endif<BR> /*<BR> * Hose scan.<BR>
*/<BR> hose->last_busno = pci_hose_scan(hose);</DIV>
<DIV><BR></DIV></SPAN></SPAN>
<DIV></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008><SPAN
class=435590206-13032008></SPAN></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008>Thanks &
Regards,</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=261510015-12032008>Vivek
Trivedi</SPAN></FONT></DIV></BODY></HTML>