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David,<br>
<br>
David Hawkins wrote:
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap="">Hi André,
</pre>
<blockquote type="cite">
<pre wrap="">I was just wondering why there's a need to define the HRCW inside a
header. This _only_ makes sense for the "HRCW from flash on local
bus"-section. Any hard coded reset word or the use of an I2C Prom
does make this obsolete.
</pre>
</blockquote>
<pre wrap=""><!---->
Right. But there is also no harm in having it :)
</pre>
</blockquote>
Yes - now I now.<br>
But it's bad feeling at first glance if compilation fails due to a
define which isn't neccessary for your config ...<br>
I've "grep"ed the code and found nothing beside the mpc83xx assembly
file - so I defined the HRCW to "0".<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap=""></pre>
<blockquote type="cite">
<pre wrap="">My fear was that the defined HRCW is actually used somewhere - which
would be a bug.
</pre>
</blockquote>
<pre wrap=""><!---->
That is true.
Code needing the values of the RCWs should be reading them
from the IMMR registers 900h (RCWLR) and 904h (RCWHR).
If you are concerned, you could have a look through the
code to check that is true.
</pre>
</blockquote>
Of course - I feared someone is using the define ...<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap=""></pre>
<blockquote type="cite">
<pre wrap="">I'm actually bringing up my latest design. It's a MPC8343B based board
stereo-camera board with external Altera FPGA on PCI and a MiniPCI Slot
for different expansion. Configuring the 512MByte Micron memory was a
little bit time consuming ... but now everything works fine.
</pre>
</blockquote>
<pre wrap=""><!---->
Great!
Since my board is a cPCI peripheral, I could cheat a little,
and program all the DDR register over PCI from an x86 host.
This allowed me to sweep the clocks (MCK and DQS), mess with
ECC, etc, until I got things right.
</pre>
</blockquote>
Running the CPU as a host gives more freedom. It's also a pitty that
there are no hard-coded HRCW for host operation :-(<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap=""></pre>
<blockquote type="cite">
<pre wrap="">My HRCW resides in a write-protected EEPROM on I2C. It's very easy with
pre-programmed EEPROMS during production ... no faults possible with
erased/invalid flash memory.
</pre>
</blockquote>
<pre wrap=""><!---->
Hmm, good point ... perhaps I'll have to use that idea ... thanks :)
</pre>
</blockquote>
Remeber to use a Prom with "extended adressing", i.e. no 24xx Microchip
etc.<br>
I'm using ROHM.<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap=""></pre>
<blockquote type="cite">
<pre wrap="">Currently I'm bringing up the two Ethernet PHYs (Vitesse VSC8601)
in RGMII mode. Communication is already established and both PHY
report valid links ... but no data yet.
Do you have experience with RGMII on MPC834x ? Any uncommon defines ?
</pre>
</blockquote>
<pre wrap=""><!---->
I've used a single PHY, but its the same as the Marvell PHYs on
the MPC8349EA-MDS-PB. I've wired it up for GMII, but I'm pretty
sure I can probably run it in DDRed RGMII mode too. I'm currently
working on UPM programming (via PCI) and writing VHDL for the
local bus UPM interface, so haven't checked out my PHY yet.
If you need a second opinion on RGMII, I can try something out
when I get to that point.
</pre>
</blockquote>
There's another thread from Tor who submitted a patch for the Vitesse
VSC8601. That's the RGMII PHY I'm using.<br>
So that'll be no problem. Communication with both PHYs is actually
working.<br>
<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap="">Best of luck with the board bring-up,
</pre>
</blockquote>
thanks :-)<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap="">Cheers,
Dave
</pre>
</blockquote>
regards,<br>
André<br>
<blockquote cite="mid:47ED68D3.2030403@ovro.caltech.edu" type="cite">
<pre wrap="">
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