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Andy Fleming schrieb:
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cite="mid:2acbd3e40804010642gbf413e1o12aa16657ce5129a@mail.gmail.com"
type="cite">
<pre wrap="">On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz
<a class="moz-txt-link-rfc2396E" href="mailto:andre.schwarz@matrix-vision.de"><andre.schwarz@matrix-vision.de></a> wrote:
</pre>
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<pre wrap="">Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
</pre>
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<pre wrap=""><!---->
If you look carefully, you'll notice that ecntrl's RPM bit is
read-only. Those bits are configured by POR pin strappings.
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sorry, my documentation (MPC8349EARM rev.1) declares this register
read-write.<br>
Of course it will be configured by the HRCW but can be overwritten
afterwards.<br>
<br>
If this is not true it's a documentation bug.<br>
<br>
<blockquote
cite="mid:2acbd3e40804010642gbf413e1o12aa16657ce5129a@mail.gmail.com"
type="cite">
<pre wrap="">You may be more familiar with the UEC, which doesn't automatically
detect the link type, but is otherwise fairly similar to the tsec.
</pre>
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What do you mean ?<br>
I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...<br>
<br>
<br>
<blockquote
cite="mid:2acbd3e40804010642gbf413e1o12aa16657ce5129a@mail.gmail.com"
type="cite">
<pre wrap="">Andy
</pre>
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<br>
<br>
regards,<br>
Andre<br>
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