<br><br><div class="gmail_quote">On Wed, May 28, 2008 at 10:24 AM, Shinose <<a href="mailto:shinose@gmail.com">shinose@gmail.com</a>> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Hi,<br><br>I am working on Nios2 custom board with intel CFI j3 flash and my data bus is only 16 bit wide. The cfi driver I have modified with asm/io calls in order to by pass the cache. But now cp.w is working and not the cp.b and cp.l . What could be the possible reason as the saveenv (writebuf) is also working fine.<br>
<br>Thanks & Regards,<br><font color="#888888">Shinose.<br>
</font></blockquote></div><br>Hi,<br><br>I got it working... it was a problem with the erase block.<br><br>Thanks & Regards,<br>Shinose.<br><br>