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<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><font size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>Kumar
Gala-3 wrote:</span></font><font size=2 face=Arial><span lang=HE dir=RTL
style='font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><span dir=LTR></span><font size=2 face=Arial><span style='font-size:
10.0pt;font-family:Arial'><span dir=LTR></span>> </span></font><font size=2
face=Arial><span lang=HE dir=RTL style='font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><span dir=LTR></span><font size=2 face=Arial><span style='font-size:
10.0pt;font-family:Arial'><span dir=LTR></span>> This is a series of patches
that are a work-in-progress towards a new</span></font><font size=2 face=Arial><span
lang=HE dir=RTL style='font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><span dir=LTR></span><font size=2 face=Arial><span style='font-size:
10.0pt;font-family:Arial'><span dir=LTR></span>> DDR initialization for the
Freescale 8{3,5,6}xxx devices that have a</span></font><font size=2 face=Arial><span
lang=HE dir=RTL style='font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><span dir=LTR></span><font size=2 face=Arial><span style='font-size:
10.0pt;font-family:Arial'><span dir=LTR></span>> common DDR controller.</span></font><font
size=2 face=Arial><span lang=HE dir=RTL style='font-size:10.0pt;font-family:
Arial'><o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><span dir=LTR></span><font size=2 face=Arial><span style='font-size:
10.0pt;font-family:Arial'><span dir=LTR></span>><o:p> </o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><font size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><font size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>Kumar,<o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><font size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>Does
this RFC also include support for identifying and initializing more than one
DDR module?<o:p></o:p></span></font></p>
<p class=MsoNormal dir=LTR style='text-align:left;direction:ltr;unicode-bidi:
embed'><font size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'>David.<o:p></o:p></span></font></p>
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