[U-Boot-Users] Interrupt management under PPC4xx platform

[llandre]

I have some questions about the interrupt management under the PPC4xx 
platform (I'm working with the 405EP evaluation board).

1) At the beginning of the boot code, the EVPR is cleared. The OpenBIOS, 
whose boot code is substantally the same, sets the EVPR to 0xFFF80000, that 
is the start address of the Flash. Why do they use such a different approach?
2) I don't understand how the code of vectors is relocated by the trap_init 
function.
Once the whole code is copied from Flash to SDRAM by the relocate_code 
function, in my understanding the code of vectors is copied again from the 
end of SDRAM to the start of SDRAM by trap_init. Here r9 is the target 
address and it set to 0x2100. So why do the interrupt_init function sets 
the EVPR to 0?



Many thanks in advance.


llandre