[U-Boot-Users] [ANNOUNCE] u-boot-ptx-20030213-1

[Geir Thomassen]

 From your patch (memsetup.S, various versions ..)

/* Step 4f: Trigger a number (usually 8) refresh cycles by     */
/*          attempting non-burst read or write accesses to disabled */
/*          SDRAM, as commonly specified in the power up sequence   */
/*          documented in SDRAM data sheets. The address(es) used   */
/*          for this purpose must not be cacheable.                 */

        ldr     r3,     =CFG_DRAM_BASE
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]


There should 9 writes, since the first write doesn't trigger a refresh 
cycle on PXA250. See Intel® PXA250 and PXA210 Processors Specification 
Update, Jan 2003, Errata #116, page 30.


.rept 9
    str     r2, [r2]
.endr


-- 
Geir