[U-Boot-Users] U-Boot hangs with L1 data cache

[Mark.Lightfoot at sita.aero]

Hello,

I've got a problem enabling the L1 data cache.  It hangs U-Boot when
enabled using the command, "dcache on".  It also hangs if I attempt to
enable the caches during U-Boot's start up.  The L1 instruction cache can
be enabled without any problem.  The code appears to hang ( ie. I lose all
console output ) when the instruction, mtspr HID0, r3, is executed in the
function, dcache_enable, which sets the DCE bit in the HID0 register.  I
don't see a problem with any of the code.  Anyone else experience this
problem and know a solution?

I'm currently porting U-Boot to the Motorola PrPMC800 board which
implements the MPC7410 processor.  At  the moment I keep all caches and
BATs disabled when U-Boot executes.  I have the code which would enable the
data cache and BATs temporarily commented out in the file,
cpu/74xx_7xx/start.S.  I did this because when I first started my porting
exercise I found code the snippet below, from cpu/74xx_7xx/start.S, caused
U-Boot to hang.  I don't need the caches enabled to boot as the board has 2
kiBytes of static ram at a fix location in memory available.  I use it to
implement the stack until SDRAM is configured instead of the stack in data
cache trick ( #define CFG_INIT_RAM_LOCK ).  I haven't even found any reason
to use the BATs as of yet.  Linux configures these for itself when it boots
anyway.

The commented out portions of the file, cpu/74xx_7xx/start.S:

      in_flash:
        ...
      #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
            /* enable address translation */
            #bl   enable_addr_trans
            #sync

            /* enable and invalidate the data cache */
            #bl   l1dcache_enable
            #sync
      #endif
      #ifdef CFG_INIT_RAM_LOCK
            bl    lock_ram_in_cache
            sync
      #endif

The code executed when the command, "dcache on", is entered, from the file,
cpu/74xx_7xx/cache.S:

_GLOBAL(dcache_enable)
      mfspr r3, HID0
      li    r5, HID0_DCFI|HID0_DLOCK
      andc  r3, r3, r5
      mtspr HID0, r3          /* no invalidate, unlock */
      ori   r3, r3, HID0_DCE
      ori   r5, r3, HID0_DCFI
      mtspr HID0, r5          /* enable + invalidate */
      mtspr HID0, r3          /* enable */
      sync
#ifdef CFG_L2
      mflr  r5
      bl    l2cache_enable          /* uses r3 and r4 */
      sync
      mtlr  r5
#endif
      blr

Regards,
Mark

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Mark Lightfoot - Software Designer - SITA
777 Walker's Line, Burlington, Ontario, Canada, L7N 2G1
905-681-5575
mark.lightfoot at sita.aero
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