[U-Boot-Users] Virtex-II Pro and Instruction Prefetching
smith at amirix.com
Sat Jun 14 14:27:14 CEST 2003
I'm working on getting PPCBoot 2.0.0 and Linux running on a custom
Virtex-II Pro development board.
I'm currently encountering problems with my DDR SDRAM controller --
it can't seem to handle instruction prefetching yet. So to sidestep the
issue for now, I want to configure the 405 so that instructions
are not prefetched.
I've disabled instruction caching altogether (ICCR = 0x00000000) and I
have a core configuration register (CCR0) value of 0x00700000, which
according to the documentation has "prefetching for non-cachable
Even so, ChipScope is telling me that instructions are still
being prefetched from SDRAM (sometimes 2 instructions, sometimes 4,
and sometimes 8 instructions at a time). Is there anything else I have
to do to disable prefetching of non-cachable instructions?
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